add fptrans support to isa caller

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 2216c04ec71235fb8a8b64f2795f2ca0e8ffb465..e0caf47c7ffbdd06a3dfa802c2ba37745675a404 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -30,7 +30,7 @@ from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
                                            OutSel, CRInSel, CROutSel, LDSTMode,
                                            SVP64RMMode, SVP64PredMode,
                                            SVP64PredInt, SVP64PredCR,
-                                           SVP64LDSTmode)
+                                           SVP64LDSTmode, FPTRANS_INSNS)
 
 from openpower.decoder.power_enums import SVPtype
 
@@ -1179,7 +1179,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
 
         # list of instructions not being supported by binutils (.long)
         dotstrp = asmop[:-1] if asmop[-1] == '.' else asmop
-        if dotstrp in [ 'fsins', 'fcoss',
+        if dotstrp in [*FPTRANS_INSNS,
                     'ffmadds', 'fdmadds', 'ffadds',
                      'mins', 'maxs', 'minu', 'maxu',
                     'setvl', 'svindex', 'svremap', 'svstep',

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 5089942ae60b204257bb1befa90c9103bf1d14df..6c71462a0683bcfedcdb5c3e515d86ecf541cd9c 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -405,6 +405,68 @@ class RegType(Enum):
     BT = CR_BIT
 
 
+FPTRANS_INSNS = (
+    "fatan2", "fatan2s",
+    "fatan2pi", "fatan2pis",
+    "fpow", "fpows",
+    "fpown", "fpowns",
+    "fpowr", "fpowrs",
+    "frootn", "frootns",
+    "fhypot", "fhypots",
+    "frsqrt", "frsqrts",
+    "fcbrt", "fcbrts",
+    "frecip", "frecips",
+    "fexp2m1", "fexp2m1s",
+    "flog2p1", "flog2p1s",
+    "fexp2", "fexp2s",
+    "flog2", "flog2s",
+    "fexpm1", "fexpm1s",
+    "flogp1", "flogp1s",
+    "fexp", "fexps",
+    "flog", "flogs",
+    "fexp10m1", "fexp10m1s",
+    "flog10p1", "flog10p1s",
+    "fexp10", "fexp10s",
+    "flog10", "flog10s",
+    "fsin", "fsins",
+    "fcos", "fcoss",
+    "ftan", "ftans",
+    "fasin", "fasins",
+    "facos", "facoss",
+    "fatan", "fatans",
+    "fsinpi", "fsinpis",
+    "fcospi", "fcospis",
+    "ftanpi", "ftanpis",
+    "fasinpi", "fasinpis",
+    "facospi", "facospis",
+    "fatanpi", "fatanpis",
+    "fsinh", "fsinhs",
+    "fcosh", "fcoshs",
+    "ftanh", "ftanhs",
+    "fasinh", "fasinhs",
+    "facosh", "facoshs",
+    "fatanh", "fatanhs",
+    "fminnum08", "fminnum08s",
+    "fmaxnum08", "fmaxnum08s",
+    "fmin19", "fmin19s",
+    "fmax19", "fmax19s",
+    "fminnum19", "fminnum19s",
+    "fmaxnum19", "fmaxnum19s",
+    "fminc", "fmincs",
+    "fmaxc", "fmaxcs",
+    "fminmagnum08", "fminmagnum08s",
+    "fmaxmagnum08", "fmaxmagnum08s",
+    "fminmag19", "fminmag19s",
+    "fmaxmag19", "fmaxmag19s",
+    "fminmagnum19", "fminmagnum19s",
+    "fmaxmagnum19", "fmaxmagnum19s",
+    "fminmagc", "fminmagcs",
+    "fmaxmagc", "fmaxmagcs",
+    "fmod", "fmods",
+    "fremainder", "fremainders",
+)
+
+
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 _insns = [
@@ -442,7 +504,6 @@ _insns = [
     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
-    "fsins", "fcoss",                                   # FP SIN/COS
     "fmvis",                                            # FP load immediate
     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
     'grev', 'grev.', 'grevi', 'grevi.',
@@ -503,6 +564,7 @@ _insns = [
     "tw", "twi",
     "wait",
     "xor", "xori", "xoris",
+    *FPTRANS_INSNS,
 ]
 
 # two-way lookup of instruction-to-index and vice-versa