add fp support to TestRunnerBase

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 8cd7db702ba5be574173e704162f643317fefa05..a2431b514dc6bfed7197dda5cf6d6535715b1eed 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -764,10 +764,11 @@ class PowerDecodeSubset(Elaboratable):
     """
 
     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
-                 svp64_en=True, regreduce_en=False):
+                 svp64_en=True, regreduce_en=False, fp_en=False):
 
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
+        self.fp_en = fp_en
         if svp64_en:
             self.is_svp64_mode = Signal()  # mark decoding as SVP64 Mode
             self.use_svp64_fft = Signal()      # FFT Mode
@@ -809,7 +810,7 @@ class PowerDecodeSubset(Elaboratable):
         if dec is None:
             dec = create_pdecode(name=fn_name, col_subset=col_subset,
                                  row_subset=row_subset,
-                                 conditions=conditions)
+                                 conditions=conditions, include_fp=fp_en)
         self.dec = dec
 
         # set up a copy of the PowerOp
@@ -1112,9 +1113,9 @@ class PowerDecode2(PowerDecodeSubset):
     """
 
     def __init__(self, dec, opkls=None, fn_name=None, final=False,
-                 state=None, svp64_en=True, regreduce_en=False):
+                 state=None, svp64_en=True, regreduce_en=False, fp_en=False):
         super().__init__(dec, opkls, fn_name, final, state, svp64_en,
-                         regreduce_en=False)
+                         regreduce_en=False, fp_en=fp_en)
         self.ldst_exc = LDSTException("dec2_exc")  # rewrites as OP_TRAP
         self.instr_fault = Signal()  # rewrites instruction as OP_FETCH_FAILED
 

diff --git a/src/openpower/test/common.py b/src/openpower/test/common.py
index 538609d3089b1d81cfdcbb1fa09718620868c314..d9a846d24de74ede5ddfa2b999fe949b80f851fe 100644 (file)
--- a/src/openpower/test/common.py
+++ b/src/openpower/test/common.py
@@ -121,6 +121,7 @@ class TestAccumulatorBase:
                  initial_svstate=0,
                  expected=None,
                  stop_at_pc=None,
+                 fpregs=None,
                  src_loc_at=0):
 
         # name of caller of this function
@@ -136,7 +137,8 @@ class TestAccumulatorBase:
                       expected=expected,
                       stop_at_pc=stop_at_pc,
                       test_file=test_file,
-                      subtest_args=self.__subtest_args.copy())
+                      subtest_args=self.__subtest_args.copy(),
+                      fpregs=fpregs)
 
         self.test_data.append(tc)
 
@@ -152,7 +154,8 @@ class TestCase:
                  expected=None,
                  stop_at_pc=None,
                  test_file=None,
-                 subtest_args=None):
+                 subtest_args=None,
+                 fpregs=None):
 
         self.program = program
         self.name = name
@@ -163,7 +166,10 @@ class TestCase:
             sprs = {}
         if mem is None:
             mem = {}
+        if fpregs is None:
+            fpregs = [0] * 32
         self.regs = regs
+        self.fpregs = fpregs
         self.sprs = sprs
         self.cr = cr
         self.mem = mem

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index a831027cf59a276033e6014b410b30622e5ae624..cf9b28b3615bae44be508337fc6e3adfe0e92beb 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -48,8 +48,10 @@ class SimRunner(StateRunner):
         self.dut = dut
 
         self.mmu = pspec.mmu == True
+        fp_en = pspec.fp_en == True
         regreduce_en = pspec.regreduce_en == True
-        self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
+        self.simdec2 = simdec2 = PowerDecode2(
+            None, regreduce_en=regreduce_en, fp_en=fp_en)
         m.submodules.simdec2 = simdec2  # pain in the neck
 
     def prepare_for_test(self, test):
@@ -71,7 +73,8 @@ class SimRunner(StateRunner):
                   disassembly=insncode,
                   bigendian=bigendian,
                   initial_svstate=test.svstate,
-                  mmu=self.mmu)
+                  mmu=self.mmu,
+                  fpregfile=test.fpregs)
 
         # run the loop of the instructions on the current test
         index = sim.pc.CIA.value//4
@@ -127,7 +130,7 @@ class TestRunnerBase(FHDLTestCase):
 
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
                  svp64=True, run_hdl=None, run_sim=True,
-                 allow_overlap=False, inorder=False):
+                 allow_overlap=False, inorder=False, fp=False):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
@@ -137,6 +140,7 @@ class TestRunnerBase(FHDLTestCase):
         self.inorder = inorder
         self.run_hdl = run_hdl
         self.run_sim = run_sim
+        self.fp = fp
 
     def run_all(self):
         m = Module()
@@ -170,7 +174,8 @@ class TestRunnerBase(FHDLTestCase):
                      allow_overlap=self.allow_overlap,
                      inorder=self.inorder,
                      mmu=self.microwatt_mmu,
-                     reg_wid=64)
+                     reg_wid=64,
+                     fp_en=self.fp)
 
         ###### SETUP PHASE #######
         # Determine the simulations needed and add to state_list

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index d7b5920c7834e4e671315dae051d17b3eb5bba6c..b9165b491e2ff41179853d4f9593746aeb134f16 100644 (file)
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -164,6 +164,10 @@ class State:
             if(reg != 0):
                 msg = "%se.intregs[%d] = 0x%x\n"
                 sout.write( msg % (lindent, i, reg))
+        for i, reg in enumerate(self.fpregs):
+            if reg != 0:
+                msg = "%se.fpregs[%d] = 0x%x\n"
+                sout.write(msg % (lindent, i, reg))
         # CR fields
         for i in range(8):
             cri = self.crregs[i]