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simplify field access
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 17 May 2020 17:10:58 +0000 (18:10 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 17 May 2020 17:17:30 +0000 (18:17 +0100)
src/soc/logical/main_stage.py patch | blob | history

diff --git a/src/soc/logical/main_stage.py b/src/soc/logical/main_stage.py
index b50afc278f0356a3eb9c51d62e4872675c1e8b7b..e740d07a55c515a8fc886eb6a6a9252515baa8f4 100644 (file)
--- a/src/soc/logical/main_stage.py
+++ b/src/soc/logical/main_stage.py
@@ -109,8 +109,7 @@ class LogicalMainStage(PipeModBase):
 
             ###### cntlz #######
             with m.Case(InternalOp.OP_CNTZ):
-                x_fields = self.fields.instrs['X']
-                XO = Signal(x_fields['XO'][0:-1].shape())
+                XO = self.fields.FormX.XO[0:-1]
                 m.submodules.countz = countz = ZeroCounter()
                 comb += countz.rs_i.eq(a)
                 comb += countz.is_32bit_i.eq(op.is_32bit)