self.assertEqual((yield partition_points[1]), True)
self.assertEqual((yield partition_points[5]), False)
yield partition_point_10.eq(0)
- yield Delay(1e-6)
+ yield Delay(0.1e-6)
self.assertEqual((yield mask), 0xFFFD)
yield partition_point_10.eq(1)
- yield Delay(1e-6)
+ yield Delay(0.1e-6)
self.assertEqual((yield mask), 0xFBFD)
sim.add_process(async_process)
(0x0000, 0xFFFF)]:
yield module.a.eq(a)
yield module.b.eq(b)
- yield Delay(1e-6)
+ yield Delay(0.1e-6)
y = 0
for mask in mask_list:
y |= mask & ((a & mask) + (b & mask))
if gen_or_check == GenOrCheck.Generate:
for i, v in zip(inputs, values):
yield i.eq(v)
- yield Delay(1e-6)
+ yield Delay(0.1e-6)
y = 0
for mask in mask_list:
v = 0
yield module.a.eq(a)
yield module.b.eq(b)
output2, intermediate_output2 = self.simd_mul(a, b, lanes)
- yield Delay(1e-6)
+ yield Delay(0.1e-6)
if gen_or_check == GenOrCheck.Check:
intermediate_output = (yield module.intermediate_output)
self.assertEqual(intermediate_output,