# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os)
-autoidx 3709
+autoidx 3702
attribute \src "libresoc.v:5.1-277.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm"
wire $0\builder_sync_rhs_array_muxed5[0:0]
attribute \src "ls180.v:7184.1-7200.4"
wire $0\builder_sync_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:133.11-133.24"
- wire width 3 $0\eint_1[2:0]
attribute \src "ls180.v:7431.1-10043.4"
wire $0\main_cmd_consumed[0:0]
attribute \src "ls180.v:7431.1-10043.4"
wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
attribute \src "ls180.v:2910.1-2956.4"
wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
- attribute \src "ls180.v:159.12-159.74"
- wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
- attribute \src "ls180.v:135.5-135.69"
- wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
- attribute \src "ls180.v:144.5-144.72"
- wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
- attribute \src "ls180.v:148.12-148.78"
- wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
- attribute \src "ls180.v:142.5-142.74"
- wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
- attribute \src "ls180.v:132.5-132.74"
- wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
attribute \src "ls180.v:2850.1-2896.4"
wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
attribute \src "ls180.v:76.5-76.46"
wire \builder_sync_rhs_array_muxed6
attribute \src "ls180.v:1898.6-1898.18"
wire \builder_wait
- attribute \src "ls180.v:11.20-11.24"
- wire width 3 output 7 \eint
- attribute \src "ls180.v:133.11-133.17"
+ attribute \src "ls180.v:31.19-31.23"
+ wire width 3 input 27 \eint
+ attribute \src "ls180.v:150.12-150.18"
wire width 3 \eint_1
- attribute \src "ls180.v:40.21-40.27"
- wire width 16 output 36 \gpio_i
- attribute \src "ls180.v:41.21-41.27"
- wire width 16 output 37 \gpio_o
- attribute \src "ls180.v:42.21-42.28"
- wire width 16 output 38 \gpio_oe
- attribute \src "ls180.v:12.14-12.21"
- wire output 8 \i2c_scl
- attribute \src "ls180.v:13.14-13.23"
- wire output 9 \i2c_sda_i
- attribute \src "ls180.v:14.14-14.23"
- wire output 10 \i2c_sda_o
- attribute \src "ls180.v:15.14-15.24"
- wire output 11 \i2c_sda_oe
+ attribute \src "ls180.v:36.20-36.26"
+ wire width 16 input 32 \gpio_i
+ attribute \src "ls180.v:37.21-37.27"
+ wire width 16 output 33 \gpio_o
+ attribute \src "ls180.v:38.21-38.28"
+ wire width 16 output 34 \gpio_oe
+ attribute \src "ls180.v:6.14-6.21"
+ wire output 2 \i2c_scl
+ attribute \src "ls180.v:7.13-7.22"
+ wire input 3 \i2c_sda_i
+ attribute \src "ls180.v:8.14-8.23"
+ wire output 4 \i2c_sda_o
+ attribute \src "ls180.v:9.14-9.24"
+ wire output 5 \i2c_sda_oe
attribute \src "ls180.v:49.13-49.21"
wire input 45 \jtag_tck
attribute \src "ls180.v:50.13-50.21"
wire width 64 \main_libresocsim_libresoc2
attribute \src "ls180.v:127.12-127.45"
wire width 2 \main_libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:159.12-159.66"
+ attribute \src "ls180.v:155.13-155.67"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
- attribute \src "ls180.v:160.13-160.67"
+ attribute \src "ls180.v:156.13-156.67"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
- attribute \src "ls180.v:161.13-161.68"
+ attribute \src "ls180.v:157.13-157.68"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
- attribute \src "ls180.v:134.6-134.61"
+ attribute \src "ls180.v:130.6-130.61"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
- attribute \src "ls180.v:135.5-135.62"
+ attribute \src "ls180.v:131.6-131.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
- attribute \src "ls180.v:136.6-136.63"
+ attribute \src "ls180.v:132.6-132.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
- attribute \src "ls180.v:137.6-137.64"
+ attribute \src "ls180.v:133.6-133.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
- attribute \src "ls180.v:143.6-143.64"
+ attribute \src "ls180.v:134.6-134.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
- attribute \src "ls180.v:144.5-144.65"
+ attribute \src "ls180.v:135.6-135.66"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
- attribute \src "ls180.v:145.6-145.66"
+ attribute \src "ls180.v:136.6-136.66"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
- attribute \src "ls180.v:146.6-146.67"
+ attribute \src "ls180.v:137.6-137.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
- attribute \src "ls180.v:147.13-147.68"
+ attribute \src "ls180.v:138.13-138.68"
wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
- attribute \src "ls180.v:156.12-156.68"
+ attribute \src "ls180.v:147.12-147.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
- attribute \src "ls180.v:153.6-153.65"
+ attribute \src "ls180.v:144.6-144.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
- attribute \src "ls180.v:155.6-155.63"
+ attribute \src "ls180.v:146.6-146.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
- attribute \src "ls180.v:154.6-154.64"
+ attribute \src "ls180.v:145.6-145.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
- attribute \src "ls180.v:157.12-157.68"
+ attribute \src "ls180.v:148.12-148.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
- attribute \src "ls180.v:148.12-148.70"
+ attribute \src "ls180.v:139.13-139.71"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
- attribute \src "ls180.v:149.13-149.71"
+ attribute \src "ls180.v:140.13-140.71"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
- attribute \src "ls180.v:150.6-150.65"
+ attribute \src "ls180.v:141.6-141.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
- attribute \src "ls180.v:152.6-152.65"
+ attribute \src "ls180.v:143.6-143.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
- attribute \src "ls180.v:151.6-151.64"
+ attribute \src "ls180.v:142.6-142.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
- attribute \src "ls180.v:139.6-139.67"
+ attribute \src "ls180.v:151.6-151.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
- attribute \src "ls180.v:141.6-141.68"
+ attribute \src "ls180.v:153.6-153.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
- attribute \src "ls180.v:142.5-142.67"
+ attribute \src "ls180.v:154.6-154.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
- attribute \src "ls180.v:140.6-140.68"
+ attribute \src "ls180.v:152.6-152.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
- attribute \src "ls180.v:129.6-129.67"
+ attribute \src "ls180.v:158.6-158.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
- attribute \src "ls180.v:131.6-131.68"
+ attribute \src "ls180.v:160.6-160.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
- attribute \src "ls180.v:132.5-132.67"
+ attribute \src "ls180.v:161.6-161.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
- attribute \src "ls180.v:130.6-130.68"
+ attribute \src "ls180.v:159.6-159.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
attribute \src "ls180.v:72.5-72.39"
wire \main_libresocsim_libresoc_dbus_ack
wire width 24 input 48 \nc
attribute \src "ls180.v:251.6-251.13"
wire \por_clk
- attribute \src "ls180.v:16.19-16.22"
- wire width 2 output 12 \pwm
- attribute \src "ls180.v:138.12-138.17"
+ attribute \src "ls180.v:5.19-5.22"
+ wire width 2 output 1 \pwm
+ attribute \src "ls180.v:129.12-129.17"
wire width 2 \pwm_1
- attribute \src "ls180.v:21.13-21.23"
- wire output 17 \sdcard_clk
- attribute \src "ls180.v:22.14-22.26"
- wire output 18 \sdcard_cmd_i
- attribute \src "ls180.v:23.13-23.25"
- wire output 19 \sdcard_cmd_o
- attribute \src "ls180.v:24.13-24.26"
- wire output 20 \sdcard_cmd_oe
- attribute \src "ls180.v:25.19-25.32"
- wire width 4 input 21 \sdcard_data_i
- attribute \src "ls180.v:26.19-26.32"
- wire width 4 output 22 \sdcard_data_o
- attribute \src "ls180.v:27.13-27.27"
- wire output 23 \sdcard_data_oe
- attribute \src "ls180.v:28.20-28.27"
- wire width 13 output 24 \sdram_a
- attribute \src "ls180.v:37.19-37.27"
- wire width 2 output 33 \sdram_ba
- attribute \src "ls180.v:34.13-34.24"
- wire output 30 \sdram_cas_n
- attribute \src "ls180.v:36.13-36.22"
- wire output 32 \sdram_cke
- attribute \src "ls180.v:39.13-39.24"
- wire output 35 \sdram_clock
- attribute \src "ls180.v:158.6-158.19"
+ attribute \src "ls180.v:10.13-10.23"
+ wire output 6 \sdcard_clk
+ attribute \src "ls180.v:11.13-11.25"
+ wire input 7 \sdcard_cmd_i
+ attribute \src "ls180.v:12.13-12.25"
+ wire output 8 \sdcard_cmd_o
+ attribute \src "ls180.v:13.13-13.26"
+ wire output 9 \sdcard_cmd_oe
+ attribute \src "ls180.v:14.19-14.32"
+ wire width 4 input 10 \sdcard_data_i
+ attribute \src "ls180.v:15.19-15.32"
+ wire width 4 output 11 \sdcard_data_o
+ attribute \src "ls180.v:16.13-16.27"
+ wire output 12 \sdcard_data_oe
+ attribute \src "ls180.v:19.20-19.27"
+ wire width 13 output 15 \sdram_a
+ attribute \src "ls180.v:28.19-28.27"
+ wire width 2 output 24 \sdram_ba
+ attribute \src "ls180.v:25.13-25.24"
+ wire output 21 \sdram_cas_n
+ attribute \src "ls180.v:27.13-27.22"
+ wire output 23 \sdram_cke
+ attribute \src "ls180.v:30.13-30.24"
+ wire output 26 \sdram_clock
+ attribute \src "ls180.v:149.6-149.19"
wire \sdram_clock_1
- attribute \src "ls180.v:35.13-35.23"
- wire output 31 \sdram_cs_n
- attribute \src "ls180.v:38.19-38.27"
- wire width 2 output 34 \sdram_dm
- attribute \src "ls180.v:29.21-29.31"
- wire width 16 output 25 \sdram_dq_i
- attribute \src "ls180.v:30.20-30.30"
- wire width 16 output 26 \sdram_dq_o
- attribute \src "ls180.v:31.13-31.24"
- wire output 27 \sdram_dq_oe
- attribute \src "ls180.v:33.13-33.24"
- wire output 29 \sdram_ras_n
- attribute \src "ls180.v:32.13-32.23"
- wire output 28 \sdram_we_n
+ attribute \src "ls180.v:26.13-26.23"
+ wire output 22 \sdram_cs_n
+ attribute \src "ls180.v:29.19-29.27"
+ wire width 2 output 25 \sdram_dm
+ attribute \src "ls180.v:20.20-20.30"
+ wire width 16 input 16 \sdram_dq_i
+ attribute \src "ls180.v:21.20-21.30"
+ wire width 16 output 17 \sdram_dq_o
+ attribute \src "ls180.v:22.13-22.24"
+ wire output 18 \sdram_dq_oe
+ attribute \src "ls180.v:24.13-24.24"
+ wire output 20 \sdram_ras_n
+ attribute \src "ls180.v:23.13-23.23"
+ wire output 19 \sdram_we_n
attribute \src "ls180.v:2647.6-2647.15"
wire \sdrio_clk
attribute \src "ls180.v:2648.6-2648.17"
wire \sdrio_clk_8
attribute \src "ls180.v:2656.6-2656.17"
wire \sdrio_clk_9
- attribute \src "ls180.v:17.13-17.26"
- wire output 13 \spimaster_clk
- attribute \src "ls180.v:19.13-19.27"
- wire output 15 \spimaster_cs_n
- attribute \src "ls180.v:20.14-20.28"
- wire output 16 \spimaster_miso
- attribute \src "ls180.v:18.13-18.27"
- wire output 14 \spimaster_mosi
- attribute \src "ls180.v:5.13-5.26"
- wire output 1 \spisdcard_clk
- attribute \src "ls180.v:7.13-7.27"
- wire output 3 \spisdcard_cs_n
- attribute \src "ls180.v:8.14-8.28"
- wire output 4 \spisdcard_miso
- attribute \src "ls180.v:6.13-6.27"
- wire output 2 \spisdcard_mosi
+ attribute \src "ls180.v:32.13-32.26"
+ wire output 28 \spimaster_clk
+ attribute \src "ls180.v:34.13-34.27"
+ wire output 30 \spimaster_cs_n
+ attribute \src "ls180.v:35.13-35.27"
+ wire input 31 \spimaster_miso
+ attribute \src "ls180.v:33.13-33.27"
+ wire output 29 \spimaster_mosi
+ attribute \src "ls180.v:39.13-39.26"
+ wire output 35 \spisdcard_clk
+ attribute \src "ls180.v:41.13-41.27"
+ wire output 37 \spisdcard_cs_n
+ attribute \src "ls180.v:42.13-42.27"
+ wire input 38 \spisdcard_miso
+ attribute \src "ls180.v:40.13-40.27"
+ wire output 36 \spisdcard_mosi
attribute \src "ls180.v:43.13-43.20"
wire input 39 \sys_clk
attribute \src "ls180.v:249.6-249.15"
wire input 40 \sys_rst
attribute \src "ls180.v:250.6-250.15"
wire \sys_rst_1
- attribute \src "ls180.v:10.13-10.20"
- wire input 6 \uart_rx
- attribute \src "ls180.v:9.13-9.20"
- wire output 5 \uart_tx
+ attribute \src "ls180.v:18.13-18.20"
+ wire input 14 \uart_rx
+ attribute \src "ls180.v:17.13-17.20"
+ wire output 13 \uart_tx
attribute \src "ls180.v:10045.12-10045.15"
memory width 32 size 128 \mem
attribute \src "ls180.v:10065.12-10065.19"
connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
end
attribute \src "ls180.v:0.0-0.0"
- process $proc$ls180.v:0$3708
+ process $proc$ls180.v:0$3701
sync always
sync init
end
attribute \src "ls180.v:1000.12-1000.47"
- process $proc$ls180.v:1000$3134
+ process $proc$ls180.v:1000$3127
assign { } { }
assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111
sync always
sync init
end
attribute \src "ls180.v:1001.5-1001.33"
- process $proc$ls180.v:1001$3135
+ process $proc$ls180.v:1001$3128
assign { } { }
assign $1\main_spimaster9_start[0:0] 1'0
sync always
update \main_spimaster9_start $1\main_spimaster9_start[0:0]
end
attribute \src "ls180.v:1003.12-1003.44"
- process $proc$ls180.v:1003$3136
+ process $proc$ls180.v:1003$3129
assign { } { }
assign $1\main_spimaster11_storage[15:0] 16'0000000000000000
sync always
update \main_spimaster11_storage $1\main_spimaster11_storage[15:0]
end
attribute \src "ls180.v:1004.5-1004.31"
- process $proc$ls180.v:1004$3137
+ process $proc$ls180.v:1004$3130
assign { } { }
assign $1\main_spimaster12_re[0:0] 1'0
sync always
sync posedge \sys_clk_1
end
attribute \src "ls180.v:1008.11-1008.42"
- process $proc$ls180.v:1008$3138
+ process $proc$ls180.v:1008$3131
assign { } { }
assign $1\main_spimaster16_storage[7:0] 8'00000000
sync always
sync posedge \sys_clk_1
end
attribute \src "ls180.v:1009.5-1009.31"
- process $proc$ls180.v:1009$3139
+ process $proc$ls180.v:1009$3132
assign { } { }
assign $1\main_spimaster17_re[0:0] 1'0
sync always
update $memwr$\storage_4$ls180.v:10126$9_EN $0$memwr$\storage_4$ls180.v:10126$9_EN[9:0]$2725
end
attribute \src "ls180.v:1013.5-1013.36"
- process $proc$ls180.v:1013$3140
+ process $proc$ls180.v:1013$3133
assign { } { }
assign $1\main_spimaster21_storage[0:0] 1'1
sync always
update \memdat_5 $0\memdat_5[9:0]
end
attribute \src "ls180.v:1014.5-1014.31"
- process $proc$ls180.v:1014$3141
+ process $proc$ls180.v:1014$3134
assign { } { }
assign $1\main_spimaster22_re[0:0] 1'0
sync always
update \memdat_7 $0\memdat_7[9:0]
end
attribute \src "ls180.v:1015.5-1015.36"
- process $proc$ls180.v:1015$3142
+ process $proc$ls180.v:1015$3135
assign { } { }
assign $1\main_spimaster23_storage[0:0] 1'0
sync always
update $memwr$\storage_6$ls180.v:10159$11_EN $0$memwr$\storage_6$ls180.v:10159$11_EN[9:0]$2739
end
attribute \src "ls180.v:1016.5-1016.31"
- process $proc$ls180.v:1016$3143
+ process $proc$ls180.v:1016$3136
assign { } { }
assign $1\main_spimaster24_re[0:0] 1'0
sync always
sync posedge \sys_clk_1
end
attribute \src "ls180.v:1017.5-1017.39"
- process $proc$ls180.v:1017$3144
+ process $proc$ls180.v:1017$3137
assign { } { }
assign $1\main_spimaster25_clk_enable[0:0] 1'0
sync always
sync posedge \sys_clk_1
end
attribute \src "ls180.v:1018.5-1018.38"
- process $proc$ls180.v:1018$3145
+ process $proc$ls180.v:1018$3138
assign { } { }
assign $1\main_spimaster26_cs_enable[0:0] 1'0
sync always
update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0]
end
attribute \src "ls180.v:1019.11-1019.40"
- process $proc$ls180.v:1019$3146
+ process $proc$ls180.v:1019$3139
assign { } { }
assign $1\main_spimaster27_count[2:0] 3'000
sync always
update \main_spimaster27_count $1\main_spimaster27_count[2:0]
end
attribute \src "ls180.v:1020.5-1020.39"
- process $proc$ls180.v:1020$3147
+ process $proc$ls180.v:1020$3140
assign { } { }
assign $1\main_spimaster28_mosi_latch[0:0] 1'0
sync always
update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0]
end
attribute \src "ls180.v:1021.5-1021.39"
- process $proc$ls180.v:1021$3148
+ process $proc$ls180.v:1021$3141
assign { } { }
assign $1\main_spimaster29_miso_latch[0:0] 1'0
sync always
update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0]
end
attribute \src "ls180.v:1022.12-1022.48"
- process $proc$ls180.v:1022$3149
+ process $proc$ls180.v:1022$3142
assign { } { }
assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000
sync always
update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0]
end
attribute \src "ls180.v:1025.11-1025.44"
- process $proc$ls180.v:1025$3150
+ process $proc$ls180.v:1025$3143
assign { } { }
assign $1\main_spimaster33_mosi_data[7:0] 8'00000000
sync always
update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0]
end
attribute \src "ls180.v:1026.11-1026.43"
- process $proc$ls180.v:1026$3151
+ process $proc$ls180.v:1026$3144
assign { } { }
assign $1\main_spimaster34_mosi_sel[2:0] 3'000
sync always
update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0]
end
attribute \src "ls180.v:1027.11-1027.44"
- process $proc$ls180.v:1027$3152
+ process $proc$ls180.v:1027$3145
assign { } { }
assign $1\main_spimaster35_miso_data[7:0] 8'00000000
sync always
update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0]
end
attribute \src "ls180.v:1030.5-1030.32"
- process $proc$ls180.v:1030$3153
+ process $proc$ls180.v:1030$3146
assign { } { }
assign $1\main_spisdcard_done0[0:0] 1'0
sync always
update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0]
end
attribute \src "ls180.v:1031.5-1031.30"
- process $proc$ls180.v:1031$3154
+ process $proc$ls180.v:1031$3147
assign { } { }
assign $1\main_spisdcard_irq[0:0] 1'0
sync always
update \main_spisdcard_irq $1\main_spisdcard_irq[0:0]
end
attribute \src "ls180.v:1033.11-1033.37"
- process $proc$ls180.v:1033$3155
+ process $proc$ls180.v:1033$3148
assign { } { }
assign $1\main_spisdcard_miso[7:0] 8'00000000
sync always
update \main_spisdcard_miso $1\main_spisdcard_miso[7:0]
end
attribute \src "ls180.v:1037.5-1037.33"
- process $proc$ls180.v:1037$3156
+ process $proc$ls180.v:1037$3149
assign { } { }
assign $1\main_spisdcard_start1[0:0] 1'0
sync always
update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0]
end
attribute \src "ls180.v:1039.12-1039.50"
- process $proc$ls180.v:1039$3157
+ process $proc$ls180.v:1039$3150
assign { } { }
assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000
sync always
update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0]
end
attribute \src "ls180.v:1040.5-1040.37"
- process $proc$ls180.v:1040$3158
+ process $proc$ls180.v:1040$3151
assign { } { }
assign $1\main_spisdcard_control_re[0:0] 1'0
sync always
update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0]
end
attribute \src "ls180.v:1044.11-1044.45"
- process $proc$ls180.v:1044$3159
+ process $proc$ls180.v:1044$3152
assign { } { }
assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000
sync always
update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0]
end
attribute \src "ls180.v:1045.5-1045.34"
- process $proc$ls180.v:1045$3160
+ process $proc$ls180.v:1045$3153
assign { } { }
assign $1\main_spisdcard_mosi_re[0:0] 1'0
sync always
update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0]
end
attribute \src "ls180.v:1049.5-1049.37"
- process $proc$ls180.v:1049$3161
+ process $proc$ls180.v:1049$3154
assign { } { }
assign $1\main_spisdcard_cs_storage[0:0] 1'1
sync always
update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0]
end
attribute \src "ls180.v:1050.5-1050.32"
- process $proc$ls180.v:1050$3162
+ process $proc$ls180.v:1050$3155
assign { } { }
assign $1\main_spisdcard_cs_re[0:0] 1'0
sync always
update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0]
end
attribute \src "ls180.v:1051.5-1051.43"
- process $proc$ls180.v:1051$3163
+ process $proc$ls180.v:1051$3156
assign { } { }
assign $1\main_spisdcard_loopback_storage[0:0] 1'0
sync always
update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0]
end
attribute \src "ls180.v:1052.5-1052.38"
- process $proc$ls180.v:1052$3164
+ process $proc$ls180.v:1052$3157
assign { } { }
assign $1\main_spisdcard_loopback_re[0:0] 1'0
sync always
update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0]
end
attribute \src "ls180.v:1053.5-1053.37"
- process $proc$ls180.v:1053$3165
+ process $proc$ls180.v:1053$3158
assign { } { }
assign $1\main_spisdcard_clk_enable[0:0] 1'0
sync always
update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0]
end
attribute \src "ls180.v:1054.5-1054.36"
- process $proc$ls180.v:1054$3166
+ process $proc$ls180.v:1054$3159
assign { } { }
assign $1\main_spisdcard_cs_enable[0:0] 1'0
sync always
update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0]
end
attribute \src "ls180.v:1055.11-1055.38"
- process $proc$ls180.v:1055$3167
+ process $proc$ls180.v:1055$3160
assign { } { }
assign $1\main_spisdcard_count[2:0] 3'000
sync always
update \main_spisdcard_count $1\main_spisdcard_count[2:0]
end
attribute \src "ls180.v:1056.5-1056.37"
- process $proc$ls180.v:1056$3168
+ process $proc$ls180.v:1056$3161
assign { } { }
assign $1\main_spisdcard_mosi_latch[0:0] 1'0
sync always
update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0]
end
attribute \src "ls180.v:1057.5-1057.37"
- process $proc$ls180.v:1057$3169
+ process $proc$ls180.v:1057$3162
assign { } { }
assign $1\main_spisdcard_miso_latch[0:0] 1'0
sync always
update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0]
end
attribute \src "ls180.v:1058.12-1058.47"
- process $proc$ls180.v:1058$3170
+ process $proc$ls180.v:1058$3163
assign { } { }
assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000
sync always
update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0]
end
attribute \src "ls180.v:1061.11-1061.42"
- process $proc$ls180.v:1061$3171
+ process $proc$ls180.v:1061$3164
assign { } { }
assign $1\main_spisdcard_mosi_data[7:0] 8'00000000
sync always
update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0]
end
attribute \src "ls180.v:1062.11-1062.41"
- process $proc$ls180.v:1062$3172
+ process $proc$ls180.v:1062$3165
assign { } { }
assign $1\main_spisdcard_mosi_sel[2:0] 3'000
sync always
update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0]
end
attribute \src "ls180.v:1063.11-1063.42"
- process $proc$ls180.v:1063$3173
+ process $proc$ls180.v:1063$3166
assign { } { }
assign $1\main_spisdcard_miso_data[7:0] 8'00000000
sync always
update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0]
end
attribute \src "ls180.v:1064.12-1064.45"
- process $proc$ls180.v:1064$3174
+ process $proc$ls180.v:1064$3167
assign { } { }
assign $1\main_spimaster1_storage[15:0] 16'0000000001111101
sync always
update \main_spimaster1_storage $1\main_spimaster1_storage[15:0]
end
attribute \src "ls180.v:1065.5-1065.30"
- process $proc$ls180.v:1065$3175
+ process $proc$ls180.v:1065$3168
assign { } { }
assign $1\main_spimaster1_re[0:0] 1'0
sync always
update \main_spimaster1_re $1\main_spimaster1_re[0:0]
end
attribute \src "ls180.v:1067.12-1067.30"
- process $proc$ls180.v:1067$3176
+ process $proc$ls180.v:1067$3169
assign { } { }
assign $1\main_dummy[23:0] 24'000000000000000000000000
sync always
update \main_dummy $1\main_dummy[23:0]
end
attribute \src "ls180.v:1071.12-1071.37"
- process $proc$ls180.v:1071$3177
+ process $proc$ls180.v:1071$3170
assign { } { }
assign $1\main_pwm0_counter[31:0] 0
sync always
update \main_pwm0_counter $1\main_pwm0_counter[31:0]
end
attribute \src "ls180.v:1072.5-1072.36"
- process $proc$ls180.v:1072$3178
+ process $proc$ls180.v:1072$3171
assign { } { }
assign $1\main_pwm0_enable_storage[0:0] 1'0
sync always
update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0]
end
attribute \src "ls180.v:1073.5-1073.31"
- process $proc$ls180.v:1073$3179
+ process $proc$ls180.v:1073$3172
assign { } { }
assign $1\main_pwm0_enable_re[0:0] 1'0
sync always
update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0]
end
attribute \src "ls180.v:1074.12-1074.43"
- process $proc$ls180.v:1074$3180
+ process $proc$ls180.v:1074$3173
assign { } { }
assign $1\main_pwm0_width_storage[31:0] 0
sync always
update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0]
end
attribute \src "ls180.v:1075.5-1075.30"
- process $proc$ls180.v:1075$3181
+ process $proc$ls180.v:1075$3174
assign { } { }
assign $1\main_pwm0_width_re[0:0] 1'0
sync always
update \main_pwm0_width_re $1\main_pwm0_width_re[0:0]
end
attribute \src "ls180.v:1076.12-1076.44"
- process $proc$ls180.v:1076$3182
+ process $proc$ls180.v:1076$3175
assign { } { }
assign $1\main_pwm0_period_storage[31:0] 0
sync always
update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0]
end
attribute \src "ls180.v:1077.5-1077.31"
- process $proc$ls180.v:1077$3183
+ process $proc$ls180.v:1077$3176
assign { } { }
assign $1\main_pwm0_period_re[0:0] 1'0
sync always
update \main_pwm0_period_re $1\main_pwm0_period_re[0:0]
end
attribute \src "ls180.v:1081.12-1081.37"
- process $proc$ls180.v:1081$3184
+ process $proc$ls180.v:1081$3177
assign { } { }
assign $1\main_pwm1_counter[31:0] 0
sync always
update \main_pwm1_counter $1\main_pwm1_counter[31:0]
end
attribute \src "ls180.v:1082.5-1082.36"
- process $proc$ls180.v:1082$3185
+ process $proc$ls180.v:1082$3178
assign { } { }
assign $1\main_pwm1_enable_storage[0:0] 1'0
sync always
update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0]
end
attribute \src "ls180.v:1083.5-1083.31"
- process $proc$ls180.v:1083$3186
+ process $proc$ls180.v:1083$3179
assign { } { }
assign $1\main_pwm1_enable_re[0:0] 1'0
sync always
update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0]
end
attribute \src "ls180.v:1084.12-1084.43"
- process $proc$ls180.v:1084$3187
+ process $proc$ls180.v:1084$3180
assign { } { }
assign $1\main_pwm1_width_storage[31:0] 0
sync always
update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0]
end
attribute \src "ls180.v:1085.5-1085.30"
- process $proc$ls180.v:1085$3188
+ process $proc$ls180.v:1085$3181
assign { } { }
assign $1\main_pwm1_width_re[0:0] 1'0
sync always
update \main_pwm1_width_re $1\main_pwm1_width_re[0:0]
end
attribute \src "ls180.v:1086.12-1086.44"
- process $proc$ls180.v:1086$3189
+ process $proc$ls180.v:1086$3182
assign { } { }
assign $1\main_pwm1_period_storage[31:0] 0
sync always
update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0]
end
attribute \src "ls180.v:1087.5-1087.31"
- process $proc$ls180.v:1087$3190
+ process $proc$ls180.v:1087$3183
assign { } { }
assign $1\main_pwm1_period_re[0:0] 1'0
sync always
update \main_pwm1_period_re $1\main_pwm1_period_re[0:0]
end
attribute \src "ls180.v:1091.11-1091.34"
- process $proc$ls180.v:1091$3191
+ process $proc$ls180.v:1091$3184
assign { } { }
assign $1\main_i2c_storage[2:0] 3'000
sync always
update \main_i2c_storage $1\main_i2c_storage[2:0]
end
attribute \src "ls180.v:1092.5-1092.23"
- process $proc$ls180.v:1092$3192
+ process $proc$ls180.v:1092$3185
assign { } { }
assign $1\main_i2c_re[0:0] 1'0
sync always
update \main_i2c_re $1\main_i2c_re[0:0]
end
attribute \src "ls180.v:1098.11-1098.46"
- process $proc$ls180.v:1098$3193
+ process $proc$ls180.v:1098$3186
assign { } { }
assign $1\main_sdphy_clocker_storage[8:0] 9'100000000
sync always
update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0]
end
attribute \src "ls180.v:1099.5-1099.33"
- process $proc$ls180.v:1099$3194
+ process $proc$ls180.v:1099$3187
assign { } { }
assign $1\main_sdphy_clocker_re[0:0] 1'0
sync always
update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0]
end
attribute \src "ls180.v:1101.5-1101.35"
- process $proc$ls180.v:1101$3195
+ process $proc$ls180.v:1101$3188
assign { } { }
assign $1\main_sdphy_clocker_clk0[0:0] 1'0
sync always
update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0]
end
attribute \src "ls180.v:1103.11-1103.41"
- process $proc$ls180.v:1103$3196
+ process $proc$ls180.v:1103$3189
assign { } { }
assign $1\main_sdphy_clocker_clks[8:0] 9'000000000
sync always
update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0]
end
attribute \src "ls180.v:1104.5-1104.35"
- process $proc$ls180.v:1104$3197
+ process $proc$ls180.v:1104$3190
assign { } { }
assign $1\main_sdphy_clocker_clk1[0:0] 1'0
sync always
update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0]
end
attribute \src "ls180.v:1105.5-1105.36"
- process $proc$ls180.v:1105$3198
+ process $proc$ls180.v:1105$3191
assign { } { }
assign $1\main_sdphy_clocker_clk_d[0:0] 1'0
sync always
update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0]
end
attribute \src "ls180.v:1109.5-1109.40"
- process $proc$ls180.v:1109$3199
+ process $proc$ls180.v:1109$3192
assign { } { }
assign $0\main_sdphy_init_initialize_w[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1114.5-1114.48"
- process $proc$ls180.v:1114$3200
+ process $proc$ls180.v:1114$3193
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1115.5-1115.50"
- process $proc$ls180.v:1115$3201
+ process $proc$ls180.v:1115$3194
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0]
end
attribute \src "ls180.v:1116.5-1116.51"
- process $proc$ls180.v:1116$3202
+ process $proc$ls180.v:1116$3195
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0]
end
attribute \src "ls180.v:1117.11-1117.57"
- process $proc$ls180.v:1117$3203
+ process $proc$ls180.v:1117$3196
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0]
end
attribute \src "ls180.v:1118.5-1118.52"
- process $proc$ls180.v:1118$3204
+ process $proc$ls180.v:1118$3197
assign { } { }
assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0]
end
attribute \src "ls180.v:1119.11-1119.39"
- process $proc$ls180.v:1119$3205
+ process $proc$ls180.v:1119$3198
assign { } { }
assign $1\main_sdphy_init_count[7:0] 8'00000000
sync always
update \main_sdphy_init_count $1\main_sdphy_init_count[7:0]
end
attribute \src "ls180.v:1124.5-1124.48"
- process $proc$ls180.v:1124$3206
+ process $proc$ls180.v:1124$3199
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1125.5-1125.50"
- process $proc$ls180.v:1125$3207
+ process $proc$ls180.v:1125$3200
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0]
end
attribute \src "ls180.v:1126.5-1126.51"
- process $proc$ls180.v:1126$3208
+ process $proc$ls180.v:1126$3201
assign { } { }
assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0]
end
attribute \src "ls180.v:1127.11-1127.57"
- process $proc$ls180.v:1127$3209
+ process $proc$ls180.v:1127$3202
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1128.5-1128.52"
- process $proc$ls180.v:1128$3210
+ process $proc$ls180.v:1128$3203
assign { } { }
assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1129.5-1129.38"
- process $proc$ls180.v:1129$3211
+ process $proc$ls180.v:1129$3204
assign { } { }
assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0
sync always
update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0]
end
attribute \src "ls180.v:1130.5-1130.38"
- process $proc$ls180.v:1130$3212
+ process $proc$ls180.v:1130$3205
assign { } { }
assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0
sync always
update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0]
end
attribute \src "ls180.v:1131.5-1131.37"
- process $proc$ls180.v:1131$3213
+ process $proc$ls180.v:1131$3206
assign { } { }
assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0]
end
attribute \src "ls180.v:1132.11-1132.51"
- process $proc$ls180.v:1132$3214
+ process $proc$ls180.v:1132$3207
assign { } { }
assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0]
end
attribute \src "ls180.v:1133.5-1133.32"
- process $proc$ls180.v:1133$3215
+ process $proc$ls180.v:1133$3208
assign { } { }
assign $1\main_sdphy_cmdw_done[0:0] 1'0
sync always
update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0]
end
attribute \src "ls180.v:1134.11-1134.39"
- process $proc$ls180.v:1134$3216
+ process $proc$ls180.v:1134$3209
assign { } { }
assign $1\main_sdphy_cmdw_count[7:0] 8'00000000
sync always
update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0]
end
attribute \src "ls180.v:1137.5-1137.49"
- process $proc$ls180.v:1137$3217
+ process $proc$ls180.v:1137$3210
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1138.5-1138.48"
- process $proc$ls180.v:1138$3218
+ process $proc$ls180.v:1138$3211
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1139.5-1139.55"
- process $proc$ls180.v:1139$3219
+ process $proc$ls180.v:1139$3212
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1141.5-1141.57"
- process $proc$ls180.v:1141$3220
+ process $proc$ls180.v:1141$3213
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1142.5-1142.58"
- process $proc$ls180.v:1142$3221
+ process $proc$ls180.v:1142$3214
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1144.11-1144.64"
- process $proc$ls180.v:1144$3222
+ process $proc$ls180.v:1144$3215
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1145.5-1145.59"
- process $proc$ls180.v:1145$3223
+ process $proc$ls180.v:1145$3216
assign { } { }
assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1147.5-1147.48"
- process $proc$ls180.v:1147$3224
+ process $proc$ls180.v:1147$3217
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1148.5-1148.50"
- process $proc$ls180.v:1148$3225
+ process $proc$ls180.v:1148$3218
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0]
end
attribute \src "ls180.v:1149.5-1149.51"
- process $proc$ls180.v:1149$3226
+ process $proc$ls180.v:1149$3219
assign { } { }
assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0
sync always
update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0]
end
attribute \src "ls180.v:1150.11-1150.57"
- process $proc$ls180.v:1150$3227
+ process $proc$ls180.v:1150$3220
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1151.5-1151.52"
- process $proc$ls180.v:1151$3228
+ process $proc$ls180.v:1151$3221
assign { } { }
assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1152.5-1152.38"
- process $proc$ls180.v:1152$3229
+ process $proc$ls180.v:1152$3222
assign { } { }
assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0
sync always
update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0]
end
attribute \src "ls180.v:1153.5-1153.38"
- process $proc$ls180.v:1153$3230
+ process $proc$ls180.v:1153$3223
assign { } { }
assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0]
end
attribute \src "ls180.v:1154.5-1154.37"
- process $proc$ls180.v:1154$3231
+ process $proc$ls180.v:1154$3224
assign { } { }
assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0]
end
attribute \src "ls180.v:1155.11-1155.53"
- process $proc$ls180.v:1155$3232
+ process $proc$ls180.v:1155$3225
assign { } { }
assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0]
end
attribute \src "ls180.v:1156.5-1156.40"
- process $proc$ls180.v:1156$3233
+ process $proc$ls180.v:1156$3226
assign { } { }
assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0
sync always
update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0]
end
attribute \src "ls180.v:1157.5-1157.40"
- process $proc$ls180.v:1157$3234
+ process $proc$ls180.v:1157$3227
assign { } { }
assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0
sync always
update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0]
end
attribute \src "ls180.v:1158.5-1158.39"
- process $proc$ls180.v:1158$3235
+ process $proc$ls180.v:1158$3228
assign { } { }
assign $1\main_sdphy_cmdr_source_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0]
end
attribute \src "ls180.v:1159.11-1159.53"
- process $proc$ls180.v:1159$3236
+ process $proc$ls180.v:1159$3229
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000
sync always
update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0]
end
attribute \src "ls180.v:1160.11-1160.55"
- process $proc$ls180.v:1160$3237
+ process $proc$ls180.v:1160$3230
assign { } { }
assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000
sync always
update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0]
end
attribute \src "ls180.v:1161.12-1161.48"
- process $proc$ls180.v:1161$3238
+ process $proc$ls180.v:1161$3231
assign { } { }
assign $1\main_sdphy_cmdr_timeout[31:0] 500000
sync always
update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0]
end
attribute \src "ls180.v:1162.11-1162.39"
- process $proc$ls180.v:1162$3239
+ process $proc$ls180.v:1162$3232
assign { } { }
assign $1\main_sdphy_cmdr_count[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0]
end
attribute \src "ls180.v:1164.5-1164.46"
- process $proc$ls180.v:1164$3240
+ process $proc$ls180.v:1164$3233
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1175.5-1175.53"
- process $proc$ls180.v:1175$3241
+ process $proc$ls180.v:1175$3234
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1180.5-1180.36"
- process $proc$ls180.v:1180$3242
+ process $proc$ls180.v:1180$3235
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0]
end
attribute \src "ls180.v:1183.5-1183.53"
- process $proc$ls180.v:1183$3243
+ process $proc$ls180.v:1183$3236
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1184.5-1184.52"
- process $proc$ls180.v:1184$3244
+ process $proc$ls180.v:1184$3237
assign { } { }
assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1188.5-1188.55"
- process $proc$ls180.v:1188$3245
+ process $proc$ls180.v:1188$3238
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0]
end
attribute \src "ls180.v:1189.5-1189.54"
- process $proc$ls180.v:1189$3246
+ process $proc$ls180.v:1189$3239
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0]
end
attribute \src "ls180.v:1190.11-1190.68"
- process $proc$ls180.v:1190$3247
+ process $proc$ls180.v:1190$3240
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1191.11-1191.81"
- process $proc$ls180.v:1191$3248
+ process $proc$ls180.v:1191$3241
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0]
end
attribute \src "ls180.v:1192.11-1192.54"
- process $proc$ls180.v:1192$3249
+ process $proc$ls180.v:1192$3242
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000
sync always
update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0]
end
attribute \src "ls180.v:1194.5-1194.53"
- process $proc$ls180.v:1194$3250
+ process $proc$ls180.v:1194$3243
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1205.5-1205.49"
- process $proc$ls180.v:1205$3251
+ process $proc$ls180.v:1205$3244
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0]
end
attribute \src "ls180.v:1207.5-1207.49"
- process $proc$ls180.v:1207$3252
+ process $proc$ls180.v:1207$3245
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0]
end
attribute \src "ls180.v:1208.5-1208.48"
- process $proc$ls180.v:1208$3253
+ process $proc$ls180.v:1208$3246
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0]
end
attribute \src "ls180.v:1209.11-1209.62"
- process $proc$ls180.v:1209$3254
+ process $proc$ls180.v:1209$3247
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0]
end
attribute \src "ls180.v:1210.5-1210.38"
- process $proc$ls180.v:1210$3255
+ process $proc$ls180.v:1210$3248
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0]
end
attribute \src "ls180.v:1215.5-1215.49"
- process $proc$ls180.v:1215$3256
+ process $proc$ls180.v:1215$3249
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1216.5-1216.51"
- process $proc$ls180.v:1216$3257
+ process $proc$ls180.v:1216$3250
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1217.5-1217.52"
- process $proc$ls180.v:1217$3258
+ process $proc$ls180.v:1217$3251
assign { } { }
assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1218.11-1218.58"
- process $proc$ls180.v:1218$3259
+ process $proc$ls180.v:1218$3252
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000
sync always
update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0]
end
attribute \src "ls180.v:1219.5-1219.53"
- process $proc$ls180.v:1219$3260
+ process $proc$ls180.v:1219$3253
assign { } { }
assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0
sync always
update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0]
end
attribute \src "ls180.v:1220.5-1220.39"
- process $proc$ls180.v:1220$3261
+ process $proc$ls180.v:1220$3254
assign { } { }
assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0]
end
attribute \src "ls180.v:1221.5-1221.39"
- process $proc$ls180.v:1221$3262
+ process $proc$ls180.v:1221$3255
assign { } { }
assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0]
end
attribute \src "ls180.v:1222.5-1222.39"
- process $proc$ls180.v:1222$3263
+ process $proc$ls180.v:1222$3256
assign { } { }
assign $1\main_sdphy_dataw_sink_first[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0]
end
attribute \src "ls180.v:1223.5-1223.38"
- process $proc$ls180.v:1223$3264
+ process $proc$ls180.v:1223$3257
assign { } { }
assign $1\main_sdphy_dataw_sink_last[0:0] 1'0
sync always
update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0]
end
attribute \src "ls180.v:1224.11-1224.52"
- process $proc$ls180.v:1224$3265
+ process $proc$ls180.v:1224$3258
assign { } { }
assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0]
end
attribute \src "ls180.v:1225.5-1225.33"
- process $proc$ls180.v:1225$3266
+ process $proc$ls180.v:1225$3259
assign { } { }
assign $1\main_sdphy_dataw_stop[0:0] 1'0
sync always
update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0]
end
attribute \src "ls180.v:1226.11-1226.40"
- process $proc$ls180.v:1226$3267
+ process $proc$ls180.v:1226$3260
assign { } { }
assign $1\main_sdphy_dataw_count[7:0] 8'00000000
sync always
update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0]
end
attribute \src "ls180.v:1227.5-1227.50"
- process $proc$ls180.v:1227$3268
+ process $proc$ls180.v:1227$3261
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1229.5-1229.50"
- process $proc$ls180.v:1229$3269
+ process $proc$ls180.v:1229$3262
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1230.5-1230.49"
- process $proc$ls180.v:1230$3270
+ process $proc$ls180.v:1230$3263
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1231.5-1231.56"
- process $proc$ls180.v:1231$3271
+ process $proc$ls180.v:1231$3264
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1232.5-1232.58"
- process $proc$ls180.v:1232$3272
+ process $proc$ls180.v:1232$3265
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1233.5-1233.58"
- process $proc$ls180.v:1233$3273
+ process $proc$ls180.v:1233$3266
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1234.5-1234.59"
- process $proc$ls180.v:1234$3274
+ process $proc$ls180.v:1234$3267
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1235.11-1235.65"
- process $proc$ls180.v:1235$3275
+ process $proc$ls180.v:1235$3268
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1236.11-1236.65"
- process $proc$ls180.v:1236$3276
+ process $proc$ls180.v:1236$3269
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1237.5-1237.60"
- process $proc$ls180.v:1237$3277
+ process $proc$ls180.v:1237$3270
assign { } { }
assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1238.5-1238.34"
- process $proc$ls180.v:1238$3278
+ process $proc$ls180.v:1238$3271
assign { } { }
assign $1\main_sdphy_dataw_start[0:0] 1'0
sync always
update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0]
end
attribute \src "ls180.v:1239.5-1239.34"
- process $proc$ls180.v:1239$3279
+ process $proc$ls180.v:1239$3272
assign { } { }
assign $1\main_sdphy_dataw_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0]
end
attribute \src "ls180.v:1240.5-1240.34"
- process $proc$ls180.v:1240$3280
+ process $proc$ls180.v:1240$3273
assign { } { }
assign $1\main_sdphy_dataw_error[0:0] 1'0
sync always
update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0]
end
attribute \src "ls180.v:1242.5-1242.47"
- process $proc$ls180.v:1242$3281
+ process $proc$ls180.v:1242$3274
assign { } { }
assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1253.5-1253.54"
- process $proc$ls180.v:1253$3282
+ process $proc$ls180.v:1253$3275
assign { } { }
assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0]
end
attribute \src "ls180.v:1258.5-1258.37"
- process $proc$ls180.v:1258$3283
+ process $proc$ls180.v:1258$3276
assign { } { }
assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0]
end
attribute \src "ls180.v:1261.5-1261.54"
- process $proc$ls180.v:1261$3284
+ process $proc$ls180.v:1261$3277
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1262.5-1262.53"
- process $proc$ls180.v:1262$3285
+ process $proc$ls180.v:1262$3278
assign { } { }
assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1266.5-1266.56"
- process $proc$ls180.v:1266$3286
+ process $proc$ls180.v:1266$3279
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0]
end
attribute \src "ls180.v:1267.5-1267.55"
- process $proc$ls180.v:1267$3287
+ process $proc$ls180.v:1267$3280
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0]
end
attribute \src "ls180.v:1268.11-1268.69"
- process $proc$ls180.v:1268$3288
+ process $proc$ls180.v:1268$3281
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1269.11-1269.82"
- process $proc$ls180.v:1269$3289
+ process $proc$ls180.v:1269$3282
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000
sync always
update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0]
end
attribute \src "ls180.v:1270.11-1270.55"
- process $proc$ls180.v:1270$3290
+ process $proc$ls180.v:1270$3283
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000
sync always
update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0]
end
attribute \src "ls180.v:1272.5-1272.54"
- process $proc$ls180.v:1272$3291
+ process $proc$ls180.v:1272$3284
assign { } { }
assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1283.5-1283.50"
- process $proc$ls180.v:1283$3292
+ process $proc$ls180.v:1283$3285
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0]
end
attribute \src "ls180.v:1285.5-1285.50"
- process $proc$ls180.v:1285$3293
+ process $proc$ls180.v:1285$3286
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0]
end
attribute \src "ls180.v:1286.5-1286.49"
- process $proc$ls180.v:1286$3294
+ process $proc$ls180.v:1286$3287
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0]
end
attribute \src "ls180.v:1287.11-1287.63"
- process $proc$ls180.v:1287$3295
+ process $proc$ls180.v:1287$3288
assign { } { }
assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0]
end
attribute \src "ls180.v:1288.5-1288.39"
- process $proc$ls180.v:1288$3296
+ process $proc$ls180.v:1288$3289
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0]
end
attribute \src "ls180.v:1291.5-1291.50"
- process $proc$ls180.v:1291$3297
+ process $proc$ls180.v:1291$3290
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1292.5-1292.49"
- process $proc$ls180.v:1292$3298
+ process $proc$ls180.v:1292$3291
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1293.5-1293.56"
- process $proc$ls180.v:1293$3299
+ process $proc$ls180.v:1293$3292
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1295.5-1295.58"
- process $proc$ls180.v:1295$3300
+ process $proc$ls180.v:1295$3293
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1296.5-1296.59"
- process $proc$ls180.v:1296$3301
+ process $proc$ls180.v:1296$3294
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1298.11-1298.65"
- process $proc$ls180.v:1298$3302
+ process $proc$ls180.v:1298$3295
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1299.5-1299.60"
- process $proc$ls180.v:1299$3303
+ process $proc$ls180.v:1299$3296
assign { } { }
assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1301.5-1301.49"
- process $proc$ls180.v:1301$3304
+ process $proc$ls180.v:1301$3297
assign { } { }
assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0
sync always
update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0]
end
attribute \src "ls180.v:1302.5-1302.51"
- process $proc$ls180.v:1302$3305
+ process $proc$ls180.v:1302$3298
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1303.5-1303.52"
- process $proc$ls180.v:1303$3306
+ process $proc$ls180.v:1303$3299
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1304.11-1304.58"
- process $proc$ls180.v:1304$3307
+ process $proc$ls180.v:1304$3300
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000
sync always
sync init
end
attribute \src "ls180.v:1305.5-1305.53"
- process $proc$ls180.v:1305$3308
+ process $proc$ls180.v:1305$3301
assign { } { }
assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1306.5-1306.39"
- process $proc$ls180.v:1306$3309
+ process $proc$ls180.v:1306$3302
assign { } { }
assign $1\main_sdphy_datar_sink_valid[0:0] 1'0
sync always
update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0]
end
attribute \src "ls180.v:1307.5-1307.39"
- process $proc$ls180.v:1307$3310
+ process $proc$ls180.v:1307$3303
assign { } { }
assign $1\main_sdphy_datar_sink_ready[0:0] 1'0
sync always
update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0]
end
attribute \src "ls180.v:1308.5-1308.38"
- process $proc$ls180.v:1308$3311
+ process $proc$ls180.v:1308$3304
assign { } { }
assign $1\main_sdphy_datar_sink_last[0:0] 1'0
sync always
update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0]
end
attribute \src "ls180.v:1309.11-1309.61"
- process $proc$ls180.v:1309$3312
+ process $proc$ls180.v:1309$3305
assign { } { }
assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000
sync always
update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0]
end
attribute \src "ls180.v:1310.5-1310.41"
- process $proc$ls180.v:1310$3313
+ process $proc$ls180.v:1310$3306
assign { } { }
assign $1\main_sdphy_datar_source_valid[0:0] 1'0
sync always
update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0]
end
attribute \src "ls180.v:1311.5-1311.41"
- process $proc$ls180.v:1311$3314
+ process $proc$ls180.v:1311$3307
assign { } { }
assign $1\main_sdphy_datar_source_ready[0:0] 1'0
sync always
update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0]
end
attribute \src "ls180.v:1312.5-1312.41"
- process $proc$ls180.v:1312$3315
+ process $proc$ls180.v:1312$3308
assign { } { }
assign $0\main_sdphy_datar_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1313.5-1313.40"
- process $proc$ls180.v:1313$3316
+ process $proc$ls180.v:1313$3309
assign { } { }
assign $1\main_sdphy_datar_source_last[0:0] 1'0
sync always
update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0]
end
attribute \src "ls180.v:1314.11-1314.54"
- process $proc$ls180.v:1314$3317
+ process $proc$ls180.v:1314$3310
assign { } { }
assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0]
end
attribute \src "ls180.v:1315.11-1315.56"
- process $proc$ls180.v:1315$3318
+ process $proc$ls180.v:1315$3311
assign { } { }
assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000
sync always
update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0]
end
attribute \src "ls180.v:1316.5-1316.33"
- process $proc$ls180.v:1316$3319
+ process $proc$ls180.v:1316$3312
assign { } { }
assign $1\main_sdphy_datar_stop[0:0] 1'0
sync always
update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0]
end
attribute \src "ls180.v:1317.12-1317.49"
- process $proc$ls180.v:1317$3320
+ process $proc$ls180.v:1317$3313
assign { } { }
assign $1\main_sdphy_datar_timeout[31:0] 500000
sync always
update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0]
end
attribute \src "ls180.v:1318.11-1318.41"
- process $proc$ls180.v:1318$3321
+ process $proc$ls180.v:1318$3314
assign { } { }
assign $1\main_sdphy_datar_count[9:0] 10'0000000000
sync always
sync init
update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
end
- attribute \src "ls180.v:132.5-132.74"
- process $proc$ls180.v:132$2775
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
- sync init
- end
attribute \src "ls180.v:1320.5-1320.48"
- process $proc$ls180.v:1320$3322
+ process $proc$ls180.v:1320$3315
assign { } { }
assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0
sync always
update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
sync init
end
- attribute \src "ls180.v:133.11-133.24"
- process $proc$ls180.v:133$2776
- assign { } { }
- assign $0\eint_1[2:0] 3'000
- sync always
- update \eint_1 $0\eint_1[2:0]
- sync init
- end
attribute \src "ls180.v:1331.5-1331.55"
- process $proc$ls180.v:1331$3323
+ process $proc$ls180.v:1331$3316
assign { } { }
assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0
sync always
update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0]
end
attribute \src "ls180.v:1336.5-1336.38"
- process $proc$ls180.v:1336$3324
+ process $proc$ls180.v:1336$3317
assign { } { }
assign $1\main_sdphy_datar_datar_run[0:0] 1'0
sync always
update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0]
end
attribute \src "ls180.v:1339.5-1339.55"
- process $proc$ls180.v:1339$3325
+ process $proc$ls180.v:1339$3318
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1340.5-1340.54"
- process $proc$ls180.v:1340$3326
+ process $proc$ls180.v:1340$3319
assign { } { }
assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1344.5-1344.57"
- process $proc$ls180.v:1344$3327
+ process $proc$ls180.v:1344$3320
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0]
end
attribute \src "ls180.v:1345.5-1345.56"
- process $proc$ls180.v:1345$3328
+ process $proc$ls180.v:1345$3321
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0]
end
attribute \src "ls180.v:1346.11-1346.70"
- process $proc$ls180.v:1346$3329
+ process $proc$ls180.v:1346$3322
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1347.11-1347.83"
- process $proc$ls180.v:1347$3330
+ process $proc$ls180.v:1347$3323
assign { } { }
assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00
sync always
update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0]
end
attribute \src "ls180.v:1348.5-1348.50"
- process $proc$ls180.v:1348$3331
+ process $proc$ls180.v:1348$3324
assign { } { }
assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0
sync always
sync init
update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0]
end
- attribute \src "ls180.v:135.5-135.69"
- process $proc$ls180.v:135$2777
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
- sync init
- end
attribute \src "ls180.v:1350.5-1350.55"
- process $proc$ls180.v:1350$3332
+ process $proc$ls180.v:1350$3325
assign { } { }
assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0
sync always
update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1361.5-1361.51"
- process $proc$ls180.v:1361$3333
+ process $proc$ls180.v:1361$3326
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0
sync always
update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0]
end
attribute \src "ls180.v:1363.5-1363.51"
- process $proc$ls180.v:1363$3334
+ process $proc$ls180.v:1363$3327
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0
sync always
update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0]
end
attribute \src "ls180.v:1364.5-1364.50"
- process $proc$ls180.v:1364$3335
+ process $proc$ls180.v:1364$3328
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0
sync always
update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0]
end
attribute \src "ls180.v:1365.11-1365.64"
- process $proc$ls180.v:1365$3336
+ process $proc$ls180.v:1365$3329
assign { } { }
assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000
sync always
update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0]
end
attribute \src "ls180.v:1366.5-1366.40"
- process $proc$ls180.v:1366$3337
+ process $proc$ls180.v:1366$3330
assign { } { }
assign $1\main_sdphy_datar_datar_reset[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0]
end
attribute \src "ls180.v:1368.5-1368.35"
- process $proc$ls180.v:1368$3338
+ process $proc$ls180.v:1368$3331
assign { } { }
assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0
sync always
update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
end
attribute \src "ls180.v:1371.11-1371.42"
- process $proc$ls180.v:1371$3339
+ process $proc$ls180.v:1371$3332
assign { } { }
assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
sync always
update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
end
attribute \src "ls180.v:1384.12-1384.52"
- process $proc$ls180.v:1384$3340
+ process $proc$ls180.v:1384$3333
assign { } { }
assign $1\main_sdcore_cmd_argument_storage[31:0] 0
sync always
update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0]
end
attribute \src "ls180.v:1385.5-1385.39"
- process $proc$ls180.v:1385$3341
+ process $proc$ls180.v:1385$3334
assign { } { }
assign $1\main_sdcore_cmd_argument_re[0:0] 1'0
sync always
update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0]
end
attribute \src "ls180.v:1386.12-1386.51"
- process $proc$ls180.v:1386$3342
+ process $proc$ls180.v:1386$3335
assign { } { }
assign $1\main_sdcore_cmd_command_storage[31:0] 0
sync always
update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0]
end
attribute \src "ls180.v:1387.5-1387.38"
- process $proc$ls180.v:1387$3343
+ process $proc$ls180.v:1387$3336
assign { } { }
assign $1\main_sdcore_cmd_command_re[0:0] 1'0
sync always
update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0]
end
attribute \src "ls180.v:1391.5-1391.34"
- process $proc$ls180.v:1391$3344
+ process $proc$ls180.v:1391$3337
assign { } { }
assign $0\main_sdcore_cmd_send_w[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1392.13-1392.53"
- process $proc$ls180.v:1392$3345
+ process $proc$ls180.v:1392$3338
assign { } { }
assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0]
end
attribute \src "ls180.v:1398.11-1398.51"
- process $proc$ls180.v:1398$3346
+ process $proc$ls180.v:1398$3339
assign { } { }
assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000
sync always
update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0]
end
attribute \src "ls180.v:1399.5-1399.39"
- process $proc$ls180.v:1399$3347
+ process $proc$ls180.v:1399$3340
assign { } { }
assign $1\main_sdcore_block_length_re[0:0] 1'0
sync always
update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
end
attribute \src "ls180.v:1400.12-1400.51"
- process $proc$ls180.v:1400$3348
+ process $proc$ls180.v:1400$3341
assign { } { }
assign $1\main_sdcore_block_count_storage[31:0] 0
sync always
update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0]
end
attribute \src "ls180.v:1401.5-1401.38"
- process $proc$ls180.v:1401$3349
+ process $proc$ls180.v:1401$3342
assign { } { }
assign $1\main_sdcore_block_count_re[0:0] 1'0
sync always
update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0]
end
attribute \src "ls180.v:1402.11-1402.51"
- process $proc$ls180.v:1402$3350
+ process $proc$ls180.v:1402$3343
assign { } { }
assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000
sync always
sync init
update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
end
- attribute \src "ls180.v:142.5-142.74"
- process $proc$ls180.v:142$2778
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
- sync init
- end
- attribute \src "ls180.v:144.5-144.72"
- process $proc$ls180.v:144$2779
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
- sync init
- end
attribute \src "ls180.v:1444.11-1444.47"
- process $proc$ls180.v:1444$3351
+ process $proc$ls180.v:1444$3344
assign { } { }
assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000
sync always
update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0]
end
attribute \src "ls180.v:1448.5-1448.49"
- process $proc$ls180.v:1448$3352
+ process $proc$ls180.v:1448$3345
assign { } { }
assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
end
attribute \src "ls180.v:1452.5-1452.51"
- process $proc$ls180.v:1452$3353
+ process $proc$ls180.v:1452$3346
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0]
end
attribute \src "ls180.v:1453.5-1453.51"
- process $proc$ls180.v:1453$3354
+ process $proc$ls180.v:1453$3347
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0]
end
attribute \src "ls180.v:1454.5-1454.51"
- process $proc$ls180.v:1454$3355
+ process $proc$ls180.v:1454$3348
assign { } { }
assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1455.5-1455.50"
- process $proc$ls180.v:1455$3356
+ process $proc$ls180.v:1455$3349
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0]
end
attribute \src "ls180.v:1456.11-1456.64"
- process $proc$ls180.v:1456$3357
+ process $proc$ls180.v:1456$3350
assign { } { }
assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0]
end
attribute \src "ls180.v:1457.11-1457.48"
- process $proc$ls180.v:1457$3358
+ process $proc$ls180.v:1457$3351
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000
sync always
update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0]
end
attribute \src "ls180.v:1458.12-1458.59"
- process $proc$ls180.v:1458$3359
+ process $proc$ls180.v:1458$3352
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0]
end
attribute \src "ls180.v:1462.12-1462.55"
- process $proc$ls180.v:1462$3360
+ process $proc$ls180.v:1462$3353
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0]
end
attribute \src "ls180.v:1465.12-1465.59"
- process $proc$ls180.v:1465$3361
+ process $proc$ls180.v:1465$3354
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0]
end
attribute \src "ls180.v:1469.12-1469.55"
- process $proc$ls180.v:1469$3362
+ process $proc$ls180.v:1469$3355
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
attribute \src "ls180.v:1472.12-1472.59"
- process $proc$ls180.v:1472$3363
+ process $proc$ls180.v:1472$3356
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0]
end
attribute \src "ls180.v:1476.12-1476.55"
- process $proc$ls180.v:1476$3364
+ process $proc$ls180.v:1476$3357
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
attribute \src "ls180.v:1479.12-1479.59"
- process $proc$ls180.v:1479$3365
+ process $proc$ls180.v:1479$3358
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000
sync always
sync init
update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0]
end
- attribute \src "ls180.v:148.12-148.78"
- process $proc$ls180.v:148$2780
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
- sync init
- end
attribute \src "ls180.v:1483.12-1483.55"
- process $proc$ls180.v:1483$3366
+ process $proc$ls180.v:1483$3359
assign { } { }
assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
attribute \src "ls180.v:1486.12-1486.54"
- process $proc$ls180.v:1486$3367
+ process $proc$ls180.v:1486$3360
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0]
end
attribute \src "ls180.v:1487.12-1487.54"
- process $proc$ls180.v:1487$3368
+ process $proc$ls180.v:1487$3361
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0]
end
attribute \src "ls180.v:1488.12-1488.54"
- process $proc$ls180.v:1488$3369
+ process $proc$ls180.v:1488$3362
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0]
end
attribute \src "ls180.v:1489.12-1489.54"
- process $proc$ls180.v:1489$3370
+ process $proc$ls180.v:1489$3363
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
end
attribute \src "ls180.v:1490.5-1490.48"
- process $proc$ls180.v:1490$3371
+ process $proc$ls180.v:1490$3364
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0]
end
attribute \src "ls180.v:1491.5-1491.48"
- process $proc$ls180.v:1491$3372
+ process $proc$ls180.v:1491$3365
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0]
end
attribute \src "ls180.v:1492.5-1492.48"
- process $proc$ls180.v:1492$3373
+ process $proc$ls180.v:1492$3366
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0]
end
attribute \src "ls180.v:1493.5-1493.47"
- process $proc$ls180.v:1493$3374
+ process $proc$ls180.v:1493$3367
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0]
end
attribute \src "ls180.v:1494.11-1494.61"
- process $proc$ls180.v:1494$3375
+ process $proc$ls180.v:1494$3368
assign { } { }
assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000
sync always
update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0]
end
attribute \src "ls180.v:1495.5-1495.50"
- process $proc$ls180.v:1495$3376
+ process $proc$ls180.v:1495$3369
assign { } { }
assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0]
end
attribute \src "ls180.v:1497.5-1497.50"
- process $proc$ls180.v:1497$3377
+ process $proc$ls180.v:1497$3370
assign { } { }
assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1500.11-1500.47"
- process $proc$ls180.v:1500$3378
+ process $proc$ls180.v:1500$3371
assign { } { }
assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000
sync always
update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0]
end
attribute \src "ls180.v:1501.11-1501.47"
- process $proc$ls180.v:1501$3379
+ process $proc$ls180.v:1501$3372
assign { } { }
assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000
sync always
update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0]
end
attribute \src "ls180.v:1502.12-1502.58"
- process $proc$ls180.v:1502$3380
+ process $proc$ls180.v:1502$3373
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0]
end
attribute \src "ls180.v:1506.12-1506.54"
- process $proc$ls180.v:1506$3381
+ process $proc$ls180.v:1506$3374
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0]
end
attribute \src "ls180.v:1507.5-1507.46"
- process $proc$ls180.v:1507$3382
+ process $proc$ls180.v:1507$3375
assign { } { }
assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0]
end
attribute \src "ls180.v:1509.12-1509.58"
- process $proc$ls180.v:1509$3383
+ process $proc$ls180.v:1509$3376
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0]
end
attribute \src "ls180.v:1513.12-1513.54"
- process $proc$ls180.v:1513$3384
+ process $proc$ls180.v:1513$3377
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0]
end
attribute \src "ls180.v:1514.5-1514.46"
- process $proc$ls180.v:1514$3385
+ process $proc$ls180.v:1514$3378
assign { } { }
assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0]
end
attribute \src "ls180.v:1516.12-1516.58"
- process $proc$ls180.v:1516$3386
+ process $proc$ls180.v:1516$3379
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0]
end
attribute \src "ls180.v:1520.12-1520.54"
- process $proc$ls180.v:1520$3387
+ process $proc$ls180.v:1520$3380
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0]
end
attribute \src "ls180.v:1521.5-1521.46"
- process $proc$ls180.v:1521$3388
+ process $proc$ls180.v:1521$3381
assign { } { }
assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0]
end
attribute \src "ls180.v:1523.12-1523.58"
- process $proc$ls180.v:1523$3389
+ process $proc$ls180.v:1523$3382
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0]
end
attribute \src "ls180.v:1527.12-1527.54"
- process $proc$ls180.v:1527$3390
+ process $proc$ls180.v:1527$3383
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0]
end
attribute \src "ls180.v:1528.5-1528.46"
- process $proc$ls180.v:1528$3391
+ process $proc$ls180.v:1528$3384
assign { } { }
assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0]
end
attribute \src "ls180.v:1530.12-1530.53"
- process $proc$ls180.v:1530$3392
+ process $proc$ls180.v:1530$3385
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0]
end
attribute \src "ls180.v:1531.12-1531.53"
- process $proc$ls180.v:1531$3393
+ process $proc$ls180.v:1531$3386
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0]
end
attribute \src "ls180.v:1532.12-1532.53"
- process $proc$ls180.v:1532$3394
+ process $proc$ls180.v:1532$3387
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0]
end
attribute \src "ls180.v:1533.12-1533.53"
- process $proc$ls180.v:1533$3395
+ process $proc$ls180.v:1533$3388
assign { } { }
assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0]
end
attribute \src "ls180.v:1534.5-1534.43"
- process $proc$ls180.v:1534$3396
+ process $proc$ls180.v:1534$3389
assign { } { }
assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0]
end
attribute \src "ls180.v:1535.12-1535.51"
- process $proc$ls180.v:1535$3397
+ process $proc$ls180.v:1535$3390
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0]
end
attribute \src "ls180.v:1536.12-1536.51"
- process $proc$ls180.v:1536$3398
+ process $proc$ls180.v:1536$3391
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0]
end
attribute \src "ls180.v:1537.12-1537.51"
- process $proc$ls180.v:1537$3399
+ process $proc$ls180.v:1537$3392
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0]
end
attribute \src "ls180.v:1538.12-1538.51"
- process $proc$ls180.v:1538$3400
+ process $proc$ls180.v:1538$3393
assign { } { }
assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
end
attribute \src "ls180.v:1540.11-1540.39"
- process $proc$ls180.v:1540$3401
+ process $proc$ls180.v:1540$3394
assign { } { }
assign $1\main_sdcore_cmd_count[2:0] 3'000
sync always
update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0]
end
attribute \src "ls180.v:1541.5-1541.32"
- process $proc$ls180.v:1541$3402
+ process $proc$ls180.v:1541$3395
assign { } { }
assign $1\main_sdcore_cmd_done[0:0] 1'0
sync always
update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0]
end
attribute \src "ls180.v:1542.5-1542.33"
- process $proc$ls180.v:1542$3403
+ process $proc$ls180.v:1542$3396
assign { } { }
assign $1\main_sdcore_cmd_error[0:0] 1'0
sync always
update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0]
end
attribute \src "ls180.v:1543.5-1543.35"
- process $proc$ls180.v:1543$3404
+ process $proc$ls180.v:1543$3397
assign { } { }
assign $1\main_sdcore_cmd_timeout[0:0] 1'0
sync always
update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0]
end
attribute \src "ls180.v:1545.12-1545.42"
- process $proc$ls180.v:1545$3405
+ process $proc$ls180.v:1545$3398
assign { } { }
assign $1\main_sdcore_data_count[31:0] 0
sync always
update \main_sdcore_data_count $1\main_sdcore_data_count[31:0]
end
attribute \src "ls180.v:1546.5-1546.33"
- process $proc$ls180.v:1546$3406
+ process $proc$ls180.v:1546$3399
assign { } { }
assign $1\main_sdcore_data_done[0:0] 1'0
sync always
update \main_sdcore_data_done $1\main_sdcore_data_done[0:0]
end
attribute \src "ls180.v:1547.5-1547.34"
- process $proc$ls180.v:1547$3407
+ process $proc$ls180.v:1547$3400
assign { } { }
assign $1\main_sdcore_data_error[0:0] 1'0
sync always
update \main_sdcore_data_error $1\main_sdcore_data_error[0:0]
end
attribute \src "ls180.v:1548.5-1548.36"
- process $proc$ls180.v:1548$3408
+ process $proc$ls180.v:1548$3401
assign { } { }
assign $1\main_sdcore_data_timeout[0:0] 1'0
sync always
update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
end
attribute \src "ls180.v:1557.11-1557.41"
- process $proc$ls180.v:1557$3409
+ process $proc$ls180.v:1557$3402
assign { } { }
assign $0\main_interface0_bus_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:1558.11-1558.41"
- process $proc$ls180.v:1558$3410
+ process $proc$ls180.v:1558$3403
assign { } { }
assign $0\main_interface0_bus_bte[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:1581.11-1581.45"
- process $proc$ls180.v:1581$3411
+ process $proc$ls180.v:1581$3404
assign { } { }
assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000
sync always
update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0]
end
attribute \src "ls180.v:1582.5-1582.41"
- process $proc$ls180.v:1582$3412
+ process $proc$ls180.v:1582$3405
assign { } { }
assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1583.11-1583.47"
- process $proc$ls180.v:1583$3413
+ process $proc$ls180.v:1583$3406
assign { } { }
assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000
sync always
update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0]
end
attribute \src "ls180.v:1584.11-1584.47"
- process $proc$ls180.v:1584$3414
+ process $proc$ls180.v:1584$3407
assign { } { }
assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000
sync always
update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0]
end
attribute \src "ls180.v:1585.11-1585.50"
- process $proc$ls180.v:1585$3415
+ process $proc$ls180.v:1585$3408
assign { } { }
assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000
sync always
sync init
update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
end
- attribute \src "ls180.v:159.12-159.74"
- process $proc$ls180.v:159$2781
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
- sync init
- end
attribute \src "ls180.v:1605.5-1605.51"
- process $proc$ls180.v:1605$3416
+ process $proc$ls180.v:1605$3409
assign { } { }
assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0
sync always
update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0]
end
attribute \src "ls180.v:1606.5-1606.50"
- process $proc$ls180.v:1606$3417
+ process $proc$ls180.v:1606$3410
assign { } { }
assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0
sync always
update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0]
end
attribute \src "ls180.v:1607.12-1607.66"
- process $proc$ls180.v:1607$3418
+ process $proc$ls180.v:1607$3411
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0
sync always
update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0]
end
attribute \src "ls180.v:1608.11-1608.77"
- process $proc$ls180.v:1608$3419
+ process $proc$ls180.v:1608$3412
assign { } { }
assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000
sync always
update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0]
end
attribute \src "ls180.v:1609.11-1609.50"
- process $proc$ls180.v:1609$3420
+ process $proc$ls180.v:1609$3413
assign { } { }
assign $1\main_sdblock2mem_converter_demux[1:0] 2'00
sync always
update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
end
attribute \src "ls180.v:1611.5-1611.49"
- process $proc$ls180.v:1611$3421
+ process $proc$ls180.v:1611$3414
assign { } { }
assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0
sync always
update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0]
end
attribute \src "ls180.v:1617.5-1617.45"
- process $proc$ls180.v:1617$3422
+ process $proc$ls180.v:1617$3415
assign { } { }
assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0
sync always
update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0]
end
attribute \src "ls180.v:1619.12-1619.62"
- process $proc$ls180.v:1619$3423
+ process $proc$ls180.v:1619$3416
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0
sync always
update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0]
end
attribute \src "ls180.v:162.12-162.71"
- process $proc$ls180.v:162$2782
+ process $proc$ls180.v:162$2775
assign { } { }
assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000
sync always
update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0]
end
attribute \src "ls180.v:1620.12-1620.60"
- process $proc$ls180.v:1620$3424
+ process $proc$ls180.v:1620$3417
assign { } { }
assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0
sync always
update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0]
end
attribute \src "ls180.v:1622.5-1622.57"
- process $proc$ls180.v:1622$3425
+ process $proc$ls180.v:1622$3418
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0]
end
attribute \src "ls180.v:1626.12-1626.67"
- process $proc$ls180.v:1626$3426
+ process $proc$ls180.v:1626$3419
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0]
end
attribute \src "ls180.v:1627.5-1627.54"
- process $proc$ls180.v:1627$3427
+ process $proc$ls180.v:1627$3420
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0]
end
attribute \src "ls180.v:1628.12-1628.69"
- process $proc$ls180.v:1628$3428
+ process $proc$ls180.v:1628$3421
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0
sync always
update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0]
end
attribute \src "ls180.v:1629.5-1629.56"
- process $proc$ls180.v:1629$3429
+ process $proc$ls180.v:1629$3422
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0]
end
attribute \src "ls180.v:163.12-163.73"
- process $proc$ls180.v:163$2783
+ process $proc$ls180.v:163$2776
assign { } { }
assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0
sync always
update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0]
end
attribute \src "ls180.v:1630.5-1630.61"
- process $proc$ls180.v:1630$3430
+ process $proc$ls180.v:1630$3423
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0]
end
attribute \src "ls180.v:1631.5-1631.56"
- process $proc$ls180.v:1631$3431
+ process $proc$ls180.v:1631$3424
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0]
end
attribute \src "ls180.v:1632.5-1632.53"
- process $proc$ls180.v:1632$3432
+ process $proc$ls180.v:1632$3425
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0]
end
attribute \src "ls180.v:1634.5-1634.59"
- process $proc$ls180.v:1634$3433
+ process $proc$ls180.v:1634$3426
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0]
end
attribute \src "ls180.v:1635.5-1635.54"
- process $proc$ls180.v:1635$3434
+ process $proc$ls180.v:1635$3427
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0]
end
attribute \src "ls180.v:1637.12-1637.61"
- process $proc$ls180.v:1637$3435
+ process $proc$ls180.v:1637$3428
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0]
end
attribute \src "ls180.v:1640.12-1640.43"
- process $proc$ls180.v:1640$3436
+ process $proc$ls180.v:1640$3429
assign { } { }
assign $1\main_interface1_bus_adr[31:0] 0
sync always
update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0]
end
attribute \src "ls180.v:1641.12-1641.45"
- process $proc$ls180.v:1641$3437
+ process $proc$ls180.v:1641$3430
assign { } { }
assign $0\main_interface1_bus_dat_w[31:0] 0
sync always
sync init
end
attribute \src "ls180.v:1643.11-1643.41"
- process $proc$ls180.v:1643$3438
+ process $proc$ls180.v:1643$3431
assign { } { }
assign $1\main_interface1_bus_sel[3:0] 4'0000
sync always
update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0]
end
attribute \src "ls180.v:1644.5-1644.35"
- process $proc$ls180.v:1644$3439
+ process $proc$ls180.v:1644$3432
assign { } { }
assign $1\main_interface1_bus_cyc[0:0] 1'0
sync always
update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0]
end
attribute \src "ls180.v:1645.5-1645.35"
- process $proc$ls180.v:1645$3440
+ process $proc$ls180.v:1645$3433
assign { } { }
assign $1\main_interface1_bus_stb[0:0] 1'0
sync always
update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0]
end
attribute \src "ls180.v:1647.5-1647.34"
- process $proc$ls180.v:1647$3441
+ process $proc$ls180.v:1647$3434
assign { } { }
assign $1\main_interface1_bus_we[0:0] 1'0
sync always
update \main_interface1_bus_we $1\main_interface1_bus_we[0:0]
end
attribute \src "ls180.v:1648.11-1648.41"
- process $proc$ls180.v:1648$3442
+ process $proc$ls180.v:1648$3435
assign { } { }
assign $0\main_interface1_bus_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:1649.11-1649.41"
- process $proc$ls180.v:1649$3443
+ process $proc$ls180.v:1649$3436
assign { } { }
assign $0\main_interface1_bus_bte[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:165.11-165.69"
- process $proc$ls180.v:165$2784
+ process $proc$ls180.v:165$2777
assign { } { }
assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000
sync always
update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0]
end
attribute \src "ls180.v:1656.5-1656.43"
- process $proc$ls180.v:1656$3444
+ process $proc$ls180.v:1656$3437
assign { } { }
assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0
sync always
update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0]
end
attribute \src "ls180.v:1657.5-1657.43"
- process $proc$ls180.v:1657$3445
+ process $proc$ls180.v:1657$3438
assign { } { }
assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0
sync always
update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0]
end
attribute \src "ls180.v:1658.5-1658.42"
- process $proc$ls180.v:1658$3446
+ process $proc$ls180.v:1658$3439
assign { } { }
assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0
sync always
update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0]
end
attribute \src "ls180.v:1659.12-1659.61"
- process $proc$ls180.v:1659$3447
+ process $proc$ls180.v:1659$3440
assign { } { }
assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0
sync always
update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0]
end
attribute \src "ls180.v:166.5-166.63"
- process $proc$ls180.v:166$2785
+ process $proc$ls180.v:166$2778
assign { } { }
assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0
sync always
update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0]
end
attribute \src "ls180.v:1660.5-1660.45"
- process $proc$ls180.v:1660$3448
+ process $proc$ls180.v:1660$3441
assign { } { }
assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0
sync always
update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0]
end
attribute \src "ls180.v:1662.5-1662.45"
- process $proc$ls180.v:1662$3449
+ process $proc$ls180.v:1662$3442
assign { } { }
assign $0\main_sdmem2block_dma_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1663.5-1663.44"
- process $proc$ls180.v:1663$3450
+ process $proc$ls180.v:1663$3443
assign { } { }
assign $1\main_sdmem2block_dma_source_last[0:0] 1'0
sync always
update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0]
end
attribute \src "ls180.v:1664.12-1664.60"
- process $proc$ls180.v:1664$3451
+ process $proc$ls180.v:1664$3444
assign { } { }
assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0
sync always
update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0]
end
attribute \src "ls180.v:1665.12-1665.45"
- process $proc$ls180.v:1665$3452
+ process $proc$ls180.v:1665$3445
assign { } { }
assign $1\main_sdmem2block_dma_data[31:0] 0
sync always
update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0]
end
attribute \src "ls180.v:1666.12-1666.53"
- process $proc$ls180.v:1666$3453
+ process $proc$ls180.v:1666$3446
assign { } { }
assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0]
end
attribute \src "ls180.v:1667.5-1667.40"
- process $proc$ls180.v:1667$3454
+ process $proc$ls180.v:1667$3447
assign { } { }
assign $1\main_sdmem2block_dma_base_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0]
end
attribute \src "ls180.v:1668.12-1668.55"
- process $proc$ls180.v:1668$3455
+ process $proc$ls180.v:1668$3448
assign { } { }
assign $1\main_sdmem2block_dma_length_storage[31:0] 0
sync always
update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0]
end
attribute \src "ls180.v:1669.5-1669.42"
- process $proc$ls180.v:1669$3456
+ process $proc$ls180.v:1669$3449
assign { } { }
assign $1\main_sdmem2block_dma_length_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0]
end
attribute \src "ls180.v:167.5-167.63"
- process $proc$ls180.v:167$2786
+ process $proc$ls180.v:167$2779
assign { } { }
assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0
sync always
update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0]
end
attribute \src "ls180.v:1670.5-1670.47"
- process $proc$ls180.v:1670$3457
+ process $proc$ls180.v:1670$3450
assign { } { }
assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0
sync always
update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0]
end
attribute \src "ls180.v:1671.5-1671.42"
- process $proc$ls180.v:1671$3458
+ process $proc$ls180.v:1671$3451
assign { } { }
assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0]
end
attribute \src "ls180.v:1672.5-1672.44"
- process $proc$ls180.v:1672$3459
+ process $proc$ls180.v:1672$3452
assign { } { }
assign $1\main_sdmem2block_dma_done_status[0:0] 1'0
sync always
update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0]
end
attribute \src "ls180.v:1674.5-1674.45"
- process $proc$ls180.v:1674$3460
+ process $proc$ls180.v:1674$3453
assign { } { }
assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0
sync always
update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0]
end
attribute \src "ls180.v:1675.5-1675.40"
- process $proc$ls180.v:1675$3461
+ process $proc$ls180.v:1675$3454
assign { } { }
assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0
sync always
update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0]
end
attribute \src "ls180.v:1679.12-1679.47"
- process $proc$ls180.v:1679$3462
+ process $proc$ls180.v:1679$3455
assign { } { }
assign $1\main_sdmem2block_dma_offset[31:0] 0
sync always
update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0]
end
attribute \src "ls180.v:169.5-169.62"
- process $proc$ls180.v:169$2787
+ process $proc$ls180.v:169$2780
assign { } { }
assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0
sync always
update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0]
end
attribute \src "ls180.v:1691.11-1691.64"
- process $proc$ls180.v:1691$3463
+ process $proc$ls180.v:1691$3456
assign { } { }
assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000
sync always
update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:1693.11-1693.48"
- process $proc$ls180.v:1693$3464
+ process $proc$ls180.v:1693$3457
assign { } { }
assign $1\main_sdmem2block_converter_mux[1:0] 2'00
sync always
update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0]
end
attribute \src "ls180.v:170.11-170.69"
- process $proc$ls180.v:170$2788
+ process $proc$ls180.v:170$2781
assign { } { }
assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:171.11-171.69"
- process $proc$ls180.v:171$2789
+ process $proc$ls180.v:171$2782
assign { } { }
assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:1717.11-1717.45"
- process $proc$ls180.v:1717$3465
+ process $proc$ls180.v:1717$3458
assign { } { }
assign $1\main_sdmem2block_fifo_level[5:0] 6'000000
sync always
update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0]
end
attribute \src "ls180.v:1718.5-1718.41"
- process $proc$ls180.v:1718$3466
+ process $proc$ls180.v:1718$3459
assign { } { }
assign $0\main_sdmem2block_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1719.11-1719.47"
- process $proc$ls180.v:1719$3467
+ process $proc$ls180.v:1719$3460
assign { } { }
assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000
sync always
update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0]
end
attribute \src "ls180.v:1720.11-1720.47"
- process $proc$ls180.v:1720$3468
+ process $proc$ls180.v:1720$3461
assign { } { }
assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000
sync always
update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0]
end
attribute \src "ls180.v:1721.11-1721.50"
- process $proc$ls180.v:1721$3469
+ process $proc$ls180.v:1721$3462
assign { } { }
assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000
sync always
update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0]
end
attribute \src "ls180.v:173.5-173.44"
- process $proc$ls180.v:173$2790
+ process $proc$ls180.v:173$2783
assign { } { }
assign $1\main_libresocsim_converter0_skip[0:0] 1'0
sync always
update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0]
end
attribute \src "ls180.v:1734.5-1734.36"
- process $proc$ls180.v:1734$3470
+ process $proc$ls180.v:1734$3463
assign { } { }
assign $1\builder_converter0_state[0:0] 1'0
sync always
update \builder_converter0_state $1\builder_converter0_state[0:0]
end
attribute \src "ls180.v:1735.5-1735.41"
- process $proc$ls180.v:1735$3471
+ process $proc$ls180.v:1735$3464
assign { } { }
assign $1\builder_converter0_next_state[0:0] 1'0
sync always
update \builder_converter0_next_state $1\builder_converter0_next_state[0:0]
end
attribute \src "ls180.v:1736.5-1736.69"
- process $proc$ls180.v:1736$3472
+ process $proc$ls180.v:1736$3465
assign { } { }
assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0
sync always
update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0]
end
attribute \src "ls180.v:1737.5-1737.72"
- process $proc$ls180.v:1737$3473
+ process $proc$ls180.v:1737$3466
assign { } { }
assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0
sync always
update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0]
end
attribute \src "ls180.v:1738.5-1738.36"
- process $proc$ls180.v:1738$3474
+ process $proc$ls180.v:1738$3467
assign { } { }
assign $1\builder_converter1_state[0:0] 1'0
sync always
update \builder_converter1_state $1\builder_converter1_state[0:0]
end
attribute \src "ls180.v:1739.5-1739.41"
- process $proc$ls180.v:1739$3475
+ process $proc$ls180.v:1739$3468
assign { } { }
assign $1\builder_converter1_next_state[0:0] 1'0
sync always
update \builder_converter1_next_state $1\builder_converter1_next_state[0:0]
end
attribute \src "ls180.v:174.5-174.47"
- process $proc$ls180.v:174$2791
+ process $proc$ls180.v:174$2784
assign { } { }
assign $1\main_libresocsim_converter0_counter[0:0] 1'0
sync always
update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0]
end
attribute \src "ls180.v:1740.5-1740.69"
- process $proc$ls180.v:1740$3476
+ process $proc$ls180.v:1740$3469
assign { } { }
assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0
sync always
update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0]
end
attribute \src "ls180.v:1741.5-1741.72"
- process $proc$ls180.v:1741$3477
+ process $proc$ls180.v:1741$3470
assign { } { }
assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0
sync always
update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0]
end
attribute \src "ls180.v:1742.5-1742.36"
- process $proc$ls180.v:1742$3478
+ process $proc$ls180.v:1742$3471
assign { } { }
assign $1\builder_converter2_state[0:0] 1'0
sync always
update \builder_converter2_state $1\builder_converter2_state[0:0]
end
attribute \src "ls180.v:1743.5-1743.41"
- process $proc$ls180.v:1743$3479
+ process $proc$ls180.v:1743$3472
assign { } { }
assign $1\builder_converter2_next_state[0:0] 1'0
sync always
update \builder_converter2_next_state $1\builder_converter2_next_state[0:0]
end
attribute \src "ls180.v:1744.5-1744.69"
- process $proc$ls180.v:1744$3480
+ process $proc$ls180.v:1744$3473
assign { } { }
assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0
sync always
update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0]
end
attribute \src "ls180.v:1745.5-1745.72"
- process $proc$ls180.v:1745$3481
+ process $proc$ls180.v:1745$3474
assign { } { }
assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0
sync always
update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0]
end
attribute \src "ls180.v:1746.11-1746.41"
- process $proc$ls180.v:1746$3482
+ process $proc$ls180.v:1746$3475
assign { } { }
assign $1\builder_refresher_state[1:0] 2'00
sync always
update \builder_refresher_state $1\builder_refresher_state[1:0]
end
attribute \src "ls180.v:1747.11-1747.46"
- process $proc$ls180.v:1747$3483
+ process $proc$ls180.v:1747$3476
assign { } { }
assign $1\builder_refresher_next_state[1:0] 2'00
sync always
update \builder_refresher_next_state $1\builder_refresher_next_state[1:0]
end
attribute \src "ls180.v:1748.11-1748.44"
- process $proc$ls180.v:1748$3484
+ process $proc$ls180.v:1748$3477
assign { } { }
assign $1\builder_bankmachine0_state[2:0] 3'000
sync always
update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0]
end
attribute \src "ls180.v:1749.11-1749.49"
- process $proc$ls180.v:1749$3485
+ process $proc$ls180.v:1749$3478
assign { } { }
assign $1\builder_bankmachine0_next_state[2:0] 3'000
sync always
update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0]
end
attribute \src "ls180.v:1750.11-1750.44"
- process $proc$ls180.v:1750$3486
+ process $proc$ls180.v:1750$3479
assign { } { }
assign $1\builder_bankmachine1_state[2:0] 3'000
sync always
update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0]
end
attribute \src "ls180.v:1751.11-1751.49"
- process $proc$ls180.v:1751$3487
+ process $proc$ls180.v:1751$3480
assign { } { }
assign $1\builder_bankmachine1_next_state[2:0] 3'000
sync always
update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0]
end
attribute \src "ls180.v:1752.11-1752.44"
- process $proc$ls180.v:1752$3488
+ process $proc$ls180.v:1752$3481
assign { } { }
assign $1\builder_bankmachine2_state[2:0] 3'000
sync always
update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0]
end
attribute \src "ls180.v:1753.11-1753.49"
- process $proc$ls180.v:1753$3489
+ process $proc$ls180.v:1753$3482
assign { } { }
assign $1\builder_bankmachine2_next_state[2:0] 3'000
sync always
update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0]
end
attribute \src "ls180.v:1754.11-1754.44"
- process $proc$ls180.v:1754$3490
+ process $proc$ls180.v:1754$3483
assign { } { }
assign $1\builder_bankmachine3_state[2:0] 3'000
sync always
update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0]
end
attribute \src "ls180.v:1755.11-1755.49"
- process $proc$ls180.v:1755$3491
+ process $proc$ls180.v:1755$3484
assign { } { }
assign $1\builder_bankmachine3_next_state[2:0] 3'000
sync always
update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0]
end
attribute \src "ls180.v:1756.11-1756.43"
- process $proc$ls180.v:1756$3492
+ process $proc$ls180.v:1756$3485
assign { } { }
assign $1\builder_multiplexer_state[2:0] 3'000
sync always
update \builder_multiplexer_state $1\builder_multiplexer_state[2:0]
end
attribute \src "ls180.v:1757.11-1757.48"
- process $proc$ls180.v:1757$3493
+ process $proc$ls180.v:1757$3486
assign { } { }
assign $1\builder_multiplexer_next_state[2:0] 3'000
sync always
update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0]
end
attribute \src "ls180.v:176.12-176.53"
- process $proc$ls180.v:176$2792
+ process $proc$ls180.v:176$2785
assign { } { }
assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0]
end
attribute \src "ls180.v:177.12-177.71"
- process $proc$ls180.v:177$2793
+ process $proc$ls180.v:177$2786
assign { } { }
assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000
sync always
update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0]
end
attribute \src "ls180.v:1770.5-1770.27"
- process $proc$ls180.v:1770$3494
+ process $proc$ls180.v:1770$3487
assign { } { }
assign $0\builder_locked0[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1771.5-1771.27"
- process $proc$ls180.v:1771$3495
+ process $proc$ls180.v:1771$3488
assign { } { }
assign $0\builder_locked1[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1772.5-1772.27"
- process $proc$ls180.v:1772$3496
+ process $proc$ls180.v:1772$3489
assign { } { }
assign $0\builder_locked2[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1773.5-1773.27"
- process $proc$ls180.v:1773$3497
+ process $proc$ls180.v:1773$3490
assign { } { }
assign $0\builder_locked3[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1774.5-1774.42"
- process $proc$ls180.v:1774$3498
+ process $proc$ls180.v:1774$3491
assign { } { }
assign $1\builder_new_master_wdata_ready[0:0] 1'0
sync always
update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0]
end
attribute \src "ls180.v:1775.5-1775.43"
- process $proc$ls180.v:1775$3499
+ process $proc$ls180.v:1775$3492
assign { } { }
assign $1\builder_new_master_rdata_valid0[0:0] 1'0
sync always
update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0]
end
attribute \src "ls180.v:1776.5-1776.43"
- process $proc$ls180.v:1776$3500
+ process $proc$ls180.v:1776$3493
assign { } { }
assign $1\builder_new_master_rdata_valid1[0:0] 1'0
sync always
update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0]
end
attribute \src "ls180.v:1777.5-1777.43"
- process $proc$ls180.v:1777$3501
+ process $proc$ls180.v:1777$3494
assign { } { }
assign $1\builder_new_master_rdata_valid2[0:0] 1'0
sync always
update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0]
end
attribute \src "ls180.v:1778.5-1778.43"
- process $proc$ls180.v:1778$3502
+ process $proc$ls180.v:1778$3495
assign { } { }
assign $1\builder_new_master_rdata_valid3[0:0] 1'0
sync always
update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0]
end
attribute \src "ls180.v:1779.5-1779.35"
- process $proc$ls180.v:1779$3503
+ process $proc$ls180.v:1779$3496
assign { } { }
assign $1\builder_converter_state[0:0] 1'0
sync always
update \builder_converter_state $1\builder_converter_state[0:0]
end
attribute \src "ls180.v:178.12-178.73"
- process $proc$ls180.v:178$2794
+ process $proc$ls180.v:178$2787
assign { } { }
assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0
sync always
update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0]
end
attribute \src "ls180.v:1780.5-1780.40"
- process $proc$ls180.v:1780$3504
+ process $proc$ls180.v:1780$3497
assign { } { }
assign $1\builder_converter_next_state[0:0] 1'0
sync always
update \builder_converter_next_state $1\builder_converter_next_state[0:0]
end
attribute \src "ls180.v:1781.5-1781.55"
- process $proc$ls180.v:1781$3505
+ process $proc$ls180.v:1781$3498
assign { } { }
assign $1\main_converter_counter_converter_next_value[0:0] 1'0
sync always
update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0]
end
attribute \src "ls180.v:1782.5-1782.58"
- process $proc$ls180.v:1782$3506
+ process $proc$ls180.v:1782$3499
assign { } { }
assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0
sync always
update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0]
end
attribute \src "ls180.v:1783.11-1783.42"
- process $proc$ls180.v:1783$3507
+ process $proc$ls180.v:1783$3500
assign { } { }
assign $1\builder_spimaster0_state[1:0] 2'00
sync always
update \builder_spimaster0_state $1\builder_spimaster0_state[1:0]
end
attribute \src "ls180.v:1784.11-1784.47"
- process $proc$ls180.v:1784$3508
+ process $proc$ls180.v:1784$3501
assign { } { }
assign $1\builder_spimaster0_next_state[1:0] 2'00
sync always
update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0]
end
attribute \src "ls180.v:1785.11-1785.62"
- process $proc$ls180.v:1785$3509
+ process $proc$ls180.v:1785$3502
assign { } { }
assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000
sync always
update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0]
end
attribute \src "ls180.v:1786.5-1786.59"
- process $proc$ls180.v:1786$3510
+ process $proc$ls180.v:1786$3503
assign { } { }
assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0
sync always
update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0]
end
attribute \src "ls180.v:1787.11-1787.42"
- process $proc$ls180.v:1787$3511
+ process $proc$ls180.v:1787$3504
assign { } { }
assign $1\builder_spimaster1_state[1:0] 2'00
sync always
update \builder_spimaster1_state $1\builder_spimaster1_state[1:0]
end
attribute \src "ls180.v:1788.11-1788.47"
- process $proc$ls180.v:1788$3512
+ process $proc$ls180.v:1788$3505
assign { } { }
assign $1\builder_spimaster1_next_state[1:0] 2'00
sync always
update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0]
end
attribute \src "ls180.v:1789.11-1789.60"
- process $proc$ls180.v:1789$3513
+ process $proc$ls180.v:1789$3506
assign { } { }
assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000
sync always
update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0]
end
attribute \src "ls180.v:1790.5-1790.57"
- process $proc$ls180.v:1790$3514
+ process $proc$ls180.v:1790$3507
assign { } { }
assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0
sync always
update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0]
end
attribute \src "ls180.v:1791.5-1791.41"
- process $proc$ls180.v:1791$3515
+ process $proc$ls180.v:1791$3508
assign { } { }
assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0
sync always
update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0]
end
attribute \src "ls180.v:1792.5-1792.46"
- process $proc$ls180.v:1792$3516
+ process $proc$ls180.v:1792$3509
assign { } { }
assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0
sync always
update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0]
end
attribute \src "ls180.v:1793.11-1793.66"
- process $proc$ls180.v:1793$3517
+ process $proc$ls180.v:1793$3510
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000
sync always
update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0]
end
attribute \src "ls180.v:1794.5-1794.63"
- process $proc$ls180.v:1794$3518
+ process $proc$ls180.v:1794$3511
assign { } { }
assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0]
end
attribute \src "ls180.v:1795.11-1795.47"
- process $proc$ls180.v:1795$3519
+ process $proc$ls180.v:1795$3512
assign { } { }
assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00
sync always
update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0]
end
attribute \src "ls180.v:1796.11-1796.52"
- process $proc$ls180.v:1796$3520
+ process $proc$ls180.v:1796$3513
assign { } { }
assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00
sync always
update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0]
end
attribute \src "ls180.v:1797.11-1797.66"
- process $proc$ls180.v:1797$3521
+ process $proc$ls180.v:1797$3514
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000
sync always
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0]
end
attribute \src "ls180.v:1798.5-1798.63"
- process $proc$ls180.v:1798$3522
+ process $proc$ls180.v:1798$3515
assign { } { }
assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
attribute \src "ls180.v:1799.11-1799.47"
- process $proc$ls180.v:1799$3523
+ process $proc$ls180.v:1799$3516
assign { } { }
assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000
sync always
update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0]
end
attribute \src "ls180.v:180.11-180.69"
- process $proc$ls180.v:180$2795
+ process $proc$ls180.v:180$2788
assign { } { }
assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000
sync always
update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0]
end
attribute \src "ls180.v:1800.11-1800.52"
- process $proc$ls180.v:1800$3524
+ process $proc$ls180.v:1800$3517
assign { } { }
assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000
sync always
update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0]
end
attribute \src "ls180.v:1801.11-1801.67"
- process $proc$ls180.v:1801$3525
+ process $proc$ls180.v:1801$3518
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000
sync always
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0]
end
attribute \src "ls180.v:1802.5-1802.64"
- process $proc$ls180.v:1802$3526
+ process $proc$ls180.v:1802$3519
assign { } { }
assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0
sync always
update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0]
end
attribute \src "ls180.v:1803.12-1803.71"
- process $proc$ls180.v:1803$3527
+ process $proc$ls180.v:1803$3520
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0
sync always
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0]
end
attribute \src "ls180.v:1804.5-1804.66"
- process $proc$ls180.v:1804$3528
+ process $proc$ls180.v:1804$3521
assign { } { }
assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0
sync always
update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0]
end
attribute \src "ls180.v:1805.5-1805.66"
- process $proc$ls180.v:1805$3529
+ process $proc$ls180.v:1805$3522
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0]
end
attribute \src "ls180.v:1806.5-1806.69"
- process $proc$ls180.v:1806$3530
+ process $proc$ls180.v:1806$3523
assign { } { }
assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0
sync always
update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0]
end
attribute \src "ls180.v:1807.5-1807.41"
- process $proc$ls180.v:1807$3531
+ process $proc$ls180.v:1807$3524
assign { } { }
assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0
sync always
update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0]
end
attribute \src "ls180.v:1808.5-1808.46"
- process $proc$ls180.v:1808$3532
+ process $proc$ls180.v:1808$3525
assign { } { }
assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0
sync always
update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0]
end
attribute \src "ls180.v:1809.5-1809.66"
- process $proc$ls180.v:1809$3533
+ process $proc$ls180.v:1809$3526
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0]
end
attribute \src "ls180.v:181.5-181.63"
- process $proc$ls180.v:181$2796
+ process $proc$ls180.v:181$2789
assign { } { }
assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0
sync always
update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0]
end
attribute \src "ls180.v:1810.5-1810.69"
- process $proc$ls180.v:1810$3534
+ process $proc$ls180.v:1810$3527
assign { } { }
assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0]
end
attribute \src "ls180.v:1811.11-1811.41"
- process $proc$ls180.v:1811$3535
+ process $proc$ls180.v:1811$3528
assign { } { }
assign $1\builder_sdphy_fsm_state[2:0] 3'000
sync always
update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0]
end
attribute \src "ls180.v:1812.11-1812.46"
- process $proc$ls180.v:1812$3536
+ process $proc$ls180.v:1812$3529
assign { } { }
assign $1\builder_sdphy_fsm_next_state[2:0] 3'000
sync always
update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0]
end
attribute \src "ls180.v:1813.11-1813.61"
- process $proc$ls180.v:1813$3537
+ process $proc$ls180.v:1813$3530
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000
sync always
update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0]
end
attribute \src "ls180.v:1814.5-1814.58"
- process $proc$ls180.v:1814$3538
+ process $proc$ls180.v:1814$3531
assign { } { }
assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0
sync always
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:1815.11-1815.48"
- process $proc$ls180.v:1815$3539
+ process $proc$ls180.v:1815$3532
assign { } { }
assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000
sync always
update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0]
end
attribute \src "ls180.v:1816.11-1816.53"
- process $proc$ls180.v:1816$3540
+ process $proc$ls180.v:1816$3533
assign { } { }
assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000
sync always
update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0]
end
attribute \src "ls180.v:1817.11-1817.70"
- process $proc$ls180.v:1817$3541
+ process $proc$ls180.v:1817$3534
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000
sync always
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0]
end
attribute \src "ls180.v:1818.5-1818.66"
- process $proc$ls180.v:1818$3542
+ process $proc$ls180.v:1818$3535
assign { } { }
assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0
sync always
update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0]
end
attribute \src "ls180.v:1819.12-1819.73"
- process $proc$ls180.v:1819$3543
+ process $proc$ls180.v:1819$3536
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0
sync always
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0]
end
attribute \src "ls180.v:182.5-182.63"
- process $proc$ls180.v:182$2797
+ process $proc$ls180.v:182$2790
assign { } { }
assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0
sync always
update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0]
end
attribute \src "ls180.v:1820.5-1820.68"
- process $proc$ls180.v:1820$3544
+ process $proc$ls180.v:1820$3537
assign { } { }
assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0
sync always
update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0]
end
attribute \src "ls180.v:1821.5-1821.69"
- process $proc$ls180.v:1821$3545
+ process $proc$ls180.v:1821$3538
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0]
end
attribute \src "ls180.v:1822.5-1822.72"
- process $proc$ls180.v:1822$3546
+ process $proc$ls180.v:1822$3539
assign { } { }
assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
attribute \src "ls180.v:1823.5-1823.52"
- process $proc$ls180.v:1823$3547
+ process $proc$ls180.v:1823$3540
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0
sync always
update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0]
end
attribute \src "ls180.v:1824.5-1824.57"
- process $proc$ls180.v:1824$3548
+ process $proc$ls180.v:1824$3541
assign { } { }
assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0
sync always
update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0]
end
attribute \src "ls180.v:1825.12-1825.93"
- process $proc$ls180.v:1825$3549
+ process $proc$ls180.v:1825$3542
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0]
end
attribute \src "ls180.v:1826.5-1826.88"
- process $proc$ls180.v:1826$3550
+ process $proc$ls180.v:1826$3543
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0]
end
attribute \src "ls180.v:1827.12-1827.93"
- process $proc$ls180.v:1827$3551
+ process $proc$ls180.v:1827$3544
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0]
end
attribute \src "ls180.v:1828.5-1828.88"
- process $proc$ls180.v:1828$3552
+ process $proc$ls180.v:1828$3545
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0]
end
attribute \src "ls180.v:1829.12-1829.93"
- process $proc$ls180.v:1829$3553
+ process $proc$ls180.v:1829$3546
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0]
end
attribute \src "ls180.v:1830.5-1830.88"
- process $proc$ls180.v:1830$3554
+ process $proc$ls180.v:1830$3547
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0]
end
attribute \src "ls180.v:1831.12-1831.93"
- process $proc$ls180.v:1831$3555
+ process $proc$ls180.v:1831$3548
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000
sync always
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0]
end
attribute \src "ls180.v:1832.5-1832.88"
- process $proc$ls180.v:1832$3556
+ process $proc$ls180.v:1832$3549
assign { } { }
assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0]
end
attribute \src "ls180.v:1833.11-1833.87"
- process $proc$ls180.v:1833$3557
+ process $proc$ls180.v:1833$3550
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000
sync always
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0]
end
attribute \src "ls180.v:1834.5-1834.84"
- process $proc$ls180.v:1834$3558
+ process $proc$ls180.v:1834$3551
assign { } { }
assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
attribute \src "ls180.v:1835.11-1835.42"
- process $proc$ls180.v:1835$3559
+ process $proc$ls180.v:1835$3552
assign { } { }
assign $1\builder_sdcore_fsm_state[2:0] 3'000
sync always
update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0]
end
attribute \src "ls180.v:1836.11-1836.47"
- process $proc$ls180.v:1836$3560
+ process $proc$ls180.v:1836$3553
assign { } { }
assign $1\builder_sdcore_fsm_next_state[2:0] 3'000
sync always
update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0]
end
attribute \src "ls180.v:1837.5-1837.55"
- process $proc$ls180.v:1837$3561
+ process $proc$ls180.v:1837$3554
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0
sync always
update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0]
end
attribute \src "ls180.v:1838.5-1838.58"
- process $proc$ls180.v:1838$3562
+ process $proc$ls180.v:1838$3555
assign { } { }
assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0
sync always
update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0]
end
attribute \src "ls180.v:1839.5-1839.56"
- process $proc$ls180.v:1839$3563
+ process $proc$ls180.v:1839$3556
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0
sync always
update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0]
end
attribute \src "ls180.v:184.5-184.62"
- process $proc$ls180.v:184$2798
+ process $proc$ls180.v:184$2791
assign { } { }
assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0
sync always
update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0]
end
attribute \src "ls180.v:1840.5-1840.59"
- process $proc$ls180.v:1840$3564
+ process $proc$ls180.v:1840$3557
assign { } { }
assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0
sync always
update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0]
end
attribute \src "ls180.v:1841.11-1841.62"
- process $proc$ls180.v:1841$3565
+ process $proc$ls180.v:1841$3558
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000
sync always
update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0]
end
attribute \src "ls180.v:1842.5-1842.59"
- process $proc$ls180.v:1842$3566
+ process $proc$ls180.v:1842$3559
assign { } { }
assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0
sync always
update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0]
end
attribute \src "ls180.v:1843.12-1843.65"
- process $proc$ls180.v:1843$3567
+ process $proc$ls180.v:1843$3560
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0
sync always
update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0]
end
attribute \src "ls180.v:1844.5-1844.60"
- process $proc$ls180.v:1844$3568
+ process $proc$ls180.v:1844$3561
assign { } { }
assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0
sync always
update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0]
end
attribute \src "ls180.v:1845.5-1845.56"
- process $proc$ls180.v:1845$3569
+ process $proc$ls180.v:1845$3562
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0
sync always
update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0]
end
attribute \src "ls180.v:1846.5-1846.59"
- process $proc$ls180.v:1846$3570
+ process $proc$ls180.v:1846$3563
assign { } { }
assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0
sync always
update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0]
end
attribute \src "ls180.v:1847.5-1847.58"
- process $proc$ls180.v:1847$3571
+ process $proc$ls180.v:1847$3564
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0
sync always
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0]
end
attribute \src "ls180.v:1848.5-1848.61"
- process $proc$ls180.v:1848$3572
+ process $proc$ls180.v:1848$3565
assign { } { }
assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0
sync always
update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0]
end
attribute \src "ls180.v:1849.5-1849.57"
- process $proc$ls180.v:1849$3573
+ process $proc$ls180.v:1849$3566
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0
sync always
update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0]
end
attribute \src "ls180.v:185.11-185.69"
- process $proc$ls180.v:185$2799
+ process $proc$ls180.v:185$2792
assign { } { }
assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:1850.5-1850.60"
- process $proc$ls180.v:1850$3574
+ process $proc$ls180.v:1850$3567
assign { } { }
assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0
sync always
update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0]
end
attribute \src "ls180.v:1851.5-1851.59"
- process $proc$ls180.v:1851$3575
+ process $proc$ls180.v:1851$3568
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0
sync always
update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0]
end
attribute \src "ls180.v:1852.5-1852.62"
- process $proc$ls180.v:1852$3576
+ process $proc$ls180.v:1852$3569
assign { } { }
assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0
sync always
update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0]
end
attribute \src "ls180.v:1853.13-1853.76"
- process $proc$ls180.v:1853$3577
+ process $proc$ls180.v:1853$3570
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0]
end
attribute \src "ls180.v:1854.5-1854.69"
- process $proc$ls180.v:1854$3578
+ process $proc$ls180.v:1854$3571
assign { } { }
assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0
sync always
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
attribute \src "ls180.v:1855.11-1855.46"
- process $proc$ls180.v:1855$3579
+ process $proc$ls180.v:1855$3572
assign { } { }
assign $1\builder_sdblock2memdma_state[1:0] 2'00
sync always
update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0]
end
attribute \src "ls180.v:1856.11-1856.51"
- process $proc$ls180.v:1856$3580
+ process $proc$ls180.v:1856$3573
assign { } { }
assign $1\builder_sdblock2memdma_next_state[1:0] 2'00
sync always
update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0]
end
attribute \src "ls180.v:1857.12-1857.87"
- process $proc$ls180.v:1857$3581
+ process $proc$ls180.v:1857$3574
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0]
end
attribute \src "ls180.v:1858.5-1858.82"
- process $proc$ls180.v:1858$3582
+ process $proc$ls180.v:1858$3575
assign { } { }
assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0
sync always
update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0]
end
attribute \src "ls180.v:1859.5-1859.44"
- process $proc$ls180.v:1859$3583
+ process $proc$ls180.v:1859$3576
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0
sync always
update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0]
end
attribute \src "ls180.v:186.11-186.69"
- process $proc$ls180.v:186$2800
+ process $proc$ls180.v:186$2793
assign { } { }
assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:1860.5-1860.49"
- process $proc$ls180.v:1860$3584
+ process $proc$ls180.v:1860$3577
assign { } { }
assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0
sync always
update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0]
end
attribute \src "ls180.v:1861.12-1861.75"
- process $proc$ls180.v:1861$3585
+ process $proc$ls180.v:1861$3578
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0
sync always
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0]
end
attribute \src "ls180.v:1862.5-1862.70"
- process $proc$ls180.v:1862$3586
+ process $proc$ls180.v:1862$3579
assign { } { }
assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0
sync always
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:1863.11-1863.60"
- process $proc$ls180.v:1863$3587
+ process $proc$ls180.v:1863$3580
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00
sync always
update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0]
end
attribute \src "ls180.v:1864.11-1864.65"
- process $proc$ls180.v:1864$3588
+ process $proc$ls180.v:1864$3581
assign { } { }
assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00
sync always
update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0]
end
attribute \src "ls180.v:1865.12-1865.87"
- process $proc$ls180.v:1865$3589
+ process $proc$ls180.v:1865$3582
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0
sync always
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0]
end
attribute \src "ls180.v:1866.5-1866.82"
- process $proc$ls180.v:1866$3590
+ process $proc$ls180.v:1866$3583
assign { } { }
assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0
sync always
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
attribute \src "ls180.v:1867.12-1867.43"
- process $proc$ls180.v:1867$3591
+ process $proc$ls180.v:1867$3584
assign { } { }
assign $1\builder_libresocsim_adr[13:0] 14'00000000000000
sync always
update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0]
end
attribute \src "ls180.v:1868.5-1868.34"
- process $proc$ls180.v:1868$3592
+ process $proc$ls180.v:1868$3585
assign { } { }
assign $1\builder_libresocsim_we[0:0] 1'0
sync always
update \builder_libresocsim_we $1\builder_libresocsim_we[0:0]
end
attribute \src "ls180.v:1869.11-1869.43"
- process $proc$ls180.v:1869$3593
+ process $proc$ls180.v:1869$3586
assign { } { }
assign $1\builder_libresocsim_dat_w[7:0] 8'00000000
sync always
update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0]
end
attribute \src "ls180.v:1873.12-1873.54"
- process $proc$ls180.v:1873$3594
+ process $proc$ls180.v:1873$3587
assign { } { }
assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0
sync always
update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0]
end
attribute \src "ls180.v:1877.5-1877.44"
- process $proc$ls180.v:1877$3595
+ process $proc$ls180.v:1877$3588
assign { } { }
assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0
sync always
update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0]
end
attribute \src "ls180.v:188.5-188.44"
- process $proc$ls180.v:188$2801
+ process $proc$ls180.v:188$2794
assign { } { }
assign $1\main_libresocsim_converter1_skip[0:0] 1'0
sync always
update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0]
end
attribute \src "ls180.v:1881.5-1881.44"
- process $proc$ls180.v:1881$3596
+ process $proc$ls180.v:1881$3589
assign { } { }
assign $0\builder_libresocsim_wishbone_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:1884.12-1884.40"
- process $proc$ls180.v:1884$3597
+ process $proc$ls180.v:1884$3590
assign { } { }
assign $1\builder_shared_dat_r[31:0] 0
sync always
update \builder_shared_dat_r $1\builder_shared_dat_r[31:0]
end
attribute \src "ls180.v:1888.5-1888.30"
- process $proc$ls180.v:1888$3598
+ process $proc$ls180.v:1888$3591
assign { } { }
assign $1\builder_shared_ack[0:0] 1'0
sync always
update \builder_shared_ack $1\builder_shared_ack[0:0]
end
attribute \src "ls180.v:189.5-189.47"
- process $proc$ls180.v:189$2802
+ process $proc$ls180.v:189$2795
assign { } { }
assign $1\main_libresocsim_converter1_counter[0:0] 1'0
sync always
update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0]
end
attribute \src "ls180.v:1894.11-1894.31"
- process $proc$ls180.v:1894$3599
+ process $proc$ls180.v:1894$3592
assign { } { }
assign $1\builder_grant[2:0] 3'000
sync always
update \builder_grant $1\builder_grant[2:0]
end
attribute \src "ls180.v:1895.11-1895.35"
- process $proc$ls180.v:1895$3600
+ process $proc$ls180.v:1895$3593
assign { } { }
assign $1\builder_slave_sel[4:0] 5'00000
sync always
update \builder_slave_sel $1\builder_slave_sel[4:0]
end
attribute \src "ls180.v:1896.11-1896.37"
- process $proc$ls180.v:1896$3601
+ process $proc$ls180.v:1896$3594
assign { } { }
assign $1\builder_slave_sel_r[4:0] 5'00000
sync always
update \builder_slave_sel_r $1\builder_slave_sel_r[4:0]
end
attribute \src "ls180.v:1897.5-1897.25"
- process $proc$ls180.v:1897$3602
+ process $proc$ls180.v:1897$3595
assign { } { }
assign $1\builder_error[0:0] 1'0
sync always
update \builder_error $1\builder_error[0:0]
end
attribute \src "ls180.v:1900.12-1900.39"
- process $proc$ls180.v:1900$3603
+ process $proc$ls180.v:1900$3596
assign { } { }
assign $1\builder_count[19:0] 20'11110100001001000000
sync always
update \builder_count $1\builder_count[19:0]
end
attribute \src "ls180.v:1904.11-1904.51"
- process $proc$ls180.v:1904$3604
+ process $proc$ls180.v:1904$3597
assign { } { }
assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:191.12-191.53"
- process $proc$ls180.v:191$2803
+ process $proc$ls180.v:191$2796
assign { } { }
assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0]
end
attribute \src "ls180.v:192.12-192.71"
- process $proc$ls180.v:192$2804
+ process $proc$ls180.v:192$2797
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000
sync always
update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0]
end
attribute \src "ls180.v:193.12-193.73"
- process $proc$ls180.v:193$2805
+ process $proc$ls180.v:193$2798
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0
sync always
update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0]
end
attribute \src "ls180.v:1945.11-1945.51"
- process $proc$ls180.v:1945$3605
+ process $proc$ls180.v:1945$3598
assign { } { }
assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:195.11-195.69"
- process $proc$ls180.v:195$2806
+ process $proc$ls180.v:195$2799
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000
sync always
update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0]
end
attribute \src "ls180.v:196.5-196.63"
- process $proc$ls180.v:196$2807
+ process $proc$ls180.v:196$2800
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0
sync always
update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0]
end
attribute \src "ls180.v:197.5-197.63"
- process $proc$ls180.v:197$2808
+ process $proc$ls180.v:197$2801
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0
sync always
update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0]
end
attribute \src "ls180.v:1974.11-1974.51"
- process $proc$ls180.v:1974$3606
+ process $proc$ls180.v:1974$3599
assign { } { }
assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:1987.11-1987.51"
- process $proc$ls180.v:1987$3607
+ process $proc$ls180.v:1987$3600
assign { } { }
assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:199.5-199.62"
- process $proc$ls180.v:199$2809
+ process $proc$ls180.v:199$2802
assign { } { }
assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0
sync always
update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0]
end
attribute \src "ls180.v:200.11-200.69"
- process $proc$ls180.v:200$2810
+ process $proc$ls180.v:200$2803
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000
sync always
sync init
end
attribute \src "ls180.v:201.11-201.69"
- process $proc$ls180.v:201$2811
+ process $proc$ls180.v:201$2804
assign { } { }
assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:2028.11-2028.51"
- process $proc$ls180.v:2028$3608
+ process $proc$ls180.v:2028$3601
assign { } { }
assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:203.5-203.44"
- process $proc$ls180.v:203$2812
+ process $proc$ls180.v:203$2805
assign { } { }
assign $1\main_libresocsim_converter2_skip[0:0] 1'0
sync always
update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0]
end
attribute \src "ls180.v:204.5-204.47"
- process $proc$ls180.v:204$2813
+ process $proc$ls180.v:204$2806
assign { } { }
assign $1\main_libresocsim_converter2_counter[0:0] 1'0
sync always
update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0]
end
attribute \src "ls180.v:206.12-206.53"
- process $proc$ls180.v:206$2814
+ process $proc$ls180.v:206$2807
assign { } { }
assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0]
end
attribute \src "ls180.v:2069.11-2069.51"
- process $proc$ls180.v:2069$3609
+ process $proc$ls180.v:2069$3602
assign { } { }
assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:213.5-213.40"
- process $proc$ls180.v:213$2815
+ process $proc$ls180.v:213$2808
assign { } { }
assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0
sync always
update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0]
end
attribute \src "ls180.v:2134.11-2134.51"
- process $proc$ls180.v:2134$3610
+ process $proc$ls180.v:2134$3603
assign { } { }
assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:217.5-217.40"
- process $proc$ls180.v:217$2816
+ process $proc$ls180.v:217$2809
assign { } { }
assign $0\main_libresocsim_ram_bus_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:220.11-220.37"
- process $proc$ls180.v:220$2817
+ process $proc$ls180.v:220$2810
assign { } { }
assign $1\main_libresocsim_we[3:0] 4'0000
sync always
update \main_libresocsim_we $1\main_libresocsim_we[3:0]
end
attribute \src "ls180.v:222.12-222.49"
- process $proc$ls180.v:222$2818
+ process $proc$ls180.v:222$2811
assign { } { }
assign $1\main_libresocsim_load_storage[31:0] 0
sync always
update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0]
end
attribute \src "ls180.v:223.5-223.36"
- process $proc$ls180.v:223$2819
+ process $proc$ls180.v:223$2812
assign { } { }
assign $1\main_libresocsim_load_re[0:0] 1'0
sync always
update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0]
end
attribute \src "ls180.v:224.12-224.51"
- process $proc$ls180.v:224$2820
+ process $proc$ls180.v:224$2813
assign { } { }
assign $1\main_libresocsim_reload_storage[31:0] 0
sync always
update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0]
end
attribute \src "ls180.v:225.5-225.38"
- process $proc$ls180.v:225$2821
+ process $proc$ls180.v:225$2814
assign { } { }
assign $1\main_libresocsim_reload_re[0:0] 1'0
sync always
update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0]
end
attribute \src "ls180.v:226.5-226.39"
- process $proc$ls180.v:226$2822
+ process $proc$ls180.v:226$2815
assign { } { }
assign $1\main_libresocsim_en_storage[0:0] 1'0
sync always
update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0]
end
attribute \src "ls180.v:2267.11-2267.51"
- process $proc$ls180.v:2267$3611
+ process $proc$ls180.v:2267$3604
assign { } { }
assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:227.5-227.34"
- process $proc$ls180.v:227$2823
+ process $proc$ls180.v:227$2816
assign { } { }
assign $1\main_libresocsim_en_re[0:0] 1'0
sync always
update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0]
end
attribute \src "ls180.v:228.5-228.49"
- process $proc$ls180.v:228$2824
+ process $proc$ls180.v:228$2817
assign { } { }
assign $1\main_libresocsim_update_value_storage[0:0] 1'0
sync always
update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0]
end
attribute \src "ls180.v:229.5-229.44"
- process $proc$ls180.v:229$2825
+ process $proc$ls180.v:229$2818
assign { } { }
assign $1\main_libresocsim_update_value_re[0:0] 1'0
sync always
update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0]
end
attribute \src "ls180.v:230.12-230.49"
- process $proc$ls180.v:230$2826
+ process $proc$ls180.v:230$2819
assign { } { }
assign $1\main_libresocsim_value_status[31:0] 0
sync always
update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0]
end
attribute \src "ls180.v:234.5-234.41"
- process $proc$ls180.v:234$2827
+ process $proc$ls180.v:234$2820
assign { } { }
assign $1\main_libresocsim_zero_pending[0:0] 1'0
sync always
update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0]
end
attribute \src "ls180.v:2348.11-2348.51"
- process $proc$ls180.v:2348$3612
+ process $proc$ls180.v:2348$3605
assign { } { }
assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:236.5-236.39"
- process $proc$ls180.v:236$2828
+ process $proc$ls180.v:236$2821
assign { } { }
assign $1\main_libresocsim_zero_clear[0:0] 1'0
sync always
update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0]
end
attribute \src "ls180.v:2365.11-2365.51"
- process $proc$ls180.v:2365$3613
+ process $proc$ls180.v:2365$3606
assign { } { }
assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:237.5-237.45"
- process $proc$ls180.v:237$2829
+ process $proc$ls180.v:237$2822
assign { } { }
assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0
sync always
update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0]
end
attribute \src "ls180.v:2406.11-2406.52"
- process $proc$ls180.v:2406$3614
+ process $proc$ls180.v:2406$3607
assign { } { }
assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2439.11-2439.52"
- process $proc$ls180.v:2439$3615
+ process $proc$ls180.v:2439$3608
assign { } { }
assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:246.5-246.49"
- process $proc$ls180.v:246$2830
+ process $proc$ls180.v:246$2823
assign { } { }
assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0
sync always
update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0]
end
attribute \src "ls180.v:247.5-247.44"
- process $proc$ls180.v:247$2831
+ process $proc$ls180.v:247$2824
assign { } { }
assign $1\main_libresocsim_eventmanager_re[0:0] 1'0
sync always
update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0]
end
attribute \src "ls180.v:248.12-248.42"
- process $proc$ls180.v:248$2832
+ process $proc$ls180.v:248$2825
assign { } { }
assign $1\main_libresocsim_value[31:0] 0
sync always
update \main_libresocsim_value $1\main_libresocsim_value[31:0]
end
attribute \src "ls180.v:2480.11-2480.52"
- process $proc$ls180.v:2480$3616
+ process $proc$ls180.v:2480$3609
assign { } { }
assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:252.5-252.24"
- process $proc$ls180.v:252$2833
+ process $proc$ls180.v:252$2826
assign { } { }
assign $1\main_int_rst[0:0] 1'1
sync always
update \main_int_rst $1\main_int_rst[0:0]
end
attribute \src "ls180.v:2545.11-2545.52"
- process $proc$ls180.v:2545$3617
+ process $proc$ls180.v:2545$3610
assign { } { }
assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2570.11-2570.52"
- process $proc$ls180.v:2570$3618
+ process $proc$ls180.v:2570$3611
assign { } { }
assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000
sync always
update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0]
end
attribute \src "ls180.v:2592.11-2592.31"
- process $proc$ls180.v:2592$3619
+ process $proc$ls180.v:2592$3612
assign { } { }
assign $1\builder_state[1:0] 2'00
sync always
update \builder_state $1\builder_state[1:0]
end
attribute \src "ls180.v:2593.11-2593.36"
- process $proc$ls180.v:2593$3620
+ process $proc$ls180.v:2593$3613
assign { } { }
assign $1\builder_next_state[1:0] 2'00
sync always
update \builder_next_state $1\builder_next_state[1:0]
end
attribute \src "ls180.v:2594.11-2594.55"
- process $proc$ls180.v:2594$3621
+ process $proc$ls180.v:2594$3614
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000
sync always
update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0]
end
attribute \src "ls180.v:2595.5-2595.52"
- process $proc$ls180.v:2595$3622
+ process $proc$ls180.v:2595$3615
assign { } { }
assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0
sync always
update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0]
end
attribute \src "ls180.v:2596.12-2596.55"
- process $proc$ls180.v:2596$3623
+ process $proc$ls180.v:2596$3616
assign { } { }
assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000
sync always
update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0]
end
attribute \src "ls180.v:2597.5-2597.50"
- process $proc$ls180.v:2597$3624
+ process $proc$ls180.v:2597$3617
assign { } { }
assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0
sync always
update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0]
end
attribute \src "ls180.v:2598.5-2598.46"
- process $proc$ls180.v:2598$3625
+ process $proc$ls180.v:2598$3618
assign { } { }
assign $1\builder_libresocsim_we_next_value2[0:0] 1'0
sync always
update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0]
end
attribute \src "ls180.v:2599.5-2599.49"
- process $proc$ls180.v:2599$3626
+ process $proc$ls180.v:2599$3619
assign { } { }
assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0
sync always
update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0]
end
attribute \src "ls180.v:2600.5-2600.41"
- process $proc$ls180.v:2600$3627
+ process $proc$ls180.v:2600$3620
assign { } { }
assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0]
end
attribute \src "ls180.v:2601.12-2601.49"
- process $proc$ls180.v:2601$3628
+ process $proc$ls180.v:2601$3621
assign { } { }
assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000
sync always
update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0]
end
attribute \src "ls180.v:2602.11-2602.47"
- process $proc$ls180.v:2602$3629
+ process $proc$ls180.v:2602$3622
assign { } { }
assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00
sync always
update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0]
end
attribute \src "ls180.v:2603.5-2603.41"
- process $proc$ls180.v:2603$3630
+ process $proc$ls180.v:2603$3623
assign { } { }
assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0]
end
attribute \src "ls180.v:2604.5-2604.41"
- process $proc$ls180.v:2604$3631
+ process $proc$ls180.v:2604$3624
assign { } { }
assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0]
end
attribute \src "ls180.v:2605.5-2605.41"
- process $proc$ls180.v:2605$3632
+ process $proc$ls180.v:2605$3625
assign { } { }
assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0]
end
attribute \src "ls180.v:2606.5-2606.39"
- process $proc$ls180.v:2606$3633
+ process $proc$ls180.v:2606$3626
assign { } { }
assign $1\builder_comb_t_array_muxed0[0:0] 1'0
sync always
update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0]
end
attribute \src "ls180.v:2607.5-2607.39"
- process $proc$ls180.v:2607$3634
+ process $proc$ls180.v:2607$3627
assign { } { }
assign $1\builder_comb_t_array_muxed1[0:0] 1'0
sync always
update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0]
end
attribute \src "ls180.v:2608.5-2608.39"
- process $proc$ls180.v:2608$3635
+ process $proc$ls180.v:2608$3628
assign { } { }
assign $1\builder_comb_t_array_muxed2[0:0] 1'0
sync always
update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0]
end
attribute \src "ls180.v:2609.5-2609.41"
- process $proc$ls180.v:2609$3636
+ process $proc$ls180.v:2609$3629
assign { } { }
assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0]
end
attribute \src "ls180.v:2610.12-2610.49"
- process $proc$ls180.v:2610$3637
+ process $proc$ls180.v:2610$3630
assign { } { }
assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000
sync always
update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0]
end
attribute \src "ls180.v:2611.11-2611.47"
- process $proc$ls180.v:2611$3638
+ process $proc$ls180.v:2611$3631
assign { } { }
assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00
sync always
update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0]
end
attribute \src "ls180.v:2612.5-2612.41"
- process $proc$ls180.v:2612$3639
+ process $proc$ls180.v:2612$3632
assign { } { }
assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0]
end
attribute \src "ls180.v:2613.5-2613.42"
- process $proc$ls180.v:2613$3640
+ process $proc$ls180.v:2613$3633
assign { } { }
assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0]
end
attribute \src "ls180.v:2614.5-2614.42"
- process $proc$ls180.v:2614$3641
+ process $proc$ls180.v:2614$3634
assign { } { }
assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0]
end
attribute \src "ls180.v:2615.5-2615.39"
- process $proc$ls180.v:2615$3642
+ process $proc$ls180.v:2615$3635
assign { } { }
assign $1\builder_comb_t_array_muxed3[0:0] 1'0
sync always
update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0]
end
attribute \src "ls180.v:2616.5-2616.39"
- process $proc$ls180.v:2616$3643
+ process $proc$ls180.v:2616$3636
assign { } { }
assign $1\builder_comb_t_array_muxed4[0:0] 1'0
sync always
update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0]
end
attribute \src "ls180.v:2617.5-2617.39"
- process $proc$ls180.v:2617$3644
+ process $proc$ls180.v:2617$3637
assign { } { }
assign $1\builder_comb_t_array_muxed5[0:0] 1'0
sync always
update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0]
end
attribute \src "ls180.v:2618.12-2618.50"
- process $proc$ls180.v:2618$3645
+ process $proc$ls180.v:2618$3638
assign { } { }
assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0]
end
attribute \src "ls180.v:2619.5-2619.42"
- process $proc$ls180.v:2619$3646
+ process $proc$ls180.v:2619$3639
assign { } { }
assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0]
end
attribute \src "ls180.v:2620.5-2620.42"
- process $proc$ls180.v:2620$3647
+ process $proc$ls180.v:2620$3640
assign { } { }
assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0]
end
attribute \src "ls180.v:2621.12-2621.50"
- process $proc$ls180.v:2621$3648
+ process $proc$ls180.v:2621$3641
assign { } { }
assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0]
end
attribute \src "ls180.v:2622.5-2622.42"
- process $proc$ls180.v:2622$3649
+ process $proc$ls180.v:2622$3642
assign { } { }
assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0]
end
attribute \src "ls180.v:2623.5-2623.42"
- process $proc$ls180.v:2623$3650
+ process $proc$ls180.v:2623$3643
assign { } { }
assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0]
end
attribute \src "ls180.v:2624.12-2624.50"
- process $proc$ls180.v:2624$3651
+ process $proc$ls180.v:2624$3644
assign { } { }
assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0]
end
attribute \src "ls180.v:2625.5-2625.42"
- process $proc$ls180.v:2625$3652
+ process $proc$ls180.v:2625$3645
assign { } { }
assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0]
end
attribute \src "ls180.v:2626.5-2626.42"
- process $proc$ls180.v:2626$3653
+ process $proc$ls180.v:2626$3646
assign { } { }
assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0]
end
attribute \src "ls180.v:2627.12-2627.50"
- process $proc$ls180.v:2627$3654
+ process $proc$ls180.v:2627$3647
assign { } { }
assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000
sync always
update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0]
end
attribute \src "ls180.v:2628.5-2628.42"
- process $proc$ls180.v:2628$3655
+ process $proc$ls180.v:2628$3648
assign { } { }
assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0]
end
attribute \src "ls180.v:2629.5-2629.42"
- process $proc$ls180.v:2629$3656
+ process $proc$ls180.v:2629$3649
assign { } { }
assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0]
end
attribute \src "ls180.v:2630.12-2630.50"
- process $proc$ls180.v:2630$3657
+ process $proc$ls180.v:2630$3650
assign { } { }
assign $1\builder_comb_rhs_array_muxed24[31:0] 0
sync always
update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0]
end
attribute \src "ls180.v:2631.12-2631.50"
- process $proc$ls180.v:2631$3658
+ process $proc$ls180.v:2631$3651
assign { } { }
assign $1\builder_comb_rhs_array_muxed25[31:0] 0
sync always
update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0]
end
attribute \src "ls180.v:2632.11-2632.48"
- process $proc$ls180.v:2632$3659
+ process $proc$ls180.v:2632$3652
assign { } { }
assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000
sync always
update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0]
end
attribute \src "ls180.v:2633.5-2633.42"
- process $proc$ls180.v:2633$3660
+ process $proc$ls180.v:2633$3653
assign { } { }
assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0]
end
attribute \src "ls180.v:2634.5-2634.42"
- process $proc$ls180.v:2634$3661
+ process $proc$ls180.v:2634$3654
assign { } { }
assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0]
end
attribute \src "ls180.v:2635.5-2635.42"
- process $proc$ls180.v:2635$3662
+ process $proc$ls180.v:2635$3655
assign { } { }
assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0]
end
attribute \src "ls180.v:2636.11-2636.48"
- process $proc$ls180.v:2636$3663
+ process $proc$ls180.v:2636$3656
assign { } { }
assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000
sync always
update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0]
end
attribute \src "ls180.v:2637.11-2637.48"
- process $proc$ls180.v:2637$3664
+ process $proc$ls180.v:2637$3657
assign { } { }
assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00
sync always
update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0]
end
attribute \src "ls180.v:2638.11-2638.47"
- process $proc$ls180.v:2638$3665
+ process $proc$ls180.v:2638$3658
assign { } { }
assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00
sync always
update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0]
end
attribute \src "ls180.v:2639.12-2639.49"
- process $proc$ls180.v:2639$3666
+ process $proc$ls180.v:2639$3659
assign { } { }
assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000
sync always
update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0]
end
attribute \src "ls180.v:2640.5-2640.41"
- process $proc$ls180.v:2640$3667
+ process $proc$ls180.v:2640$3660
assign { } { }
assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0]
end
attribute \src "ls180.v:2641.5-2641.41"
- process $proc$ls180.v:2641$3668
+ process $proc$ls180.v:2641$3661
assign { } { }
assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0]
end
attribute \src "ls180.v:2642.5-2642.41"
- process $proc$ls180.v:2642$3669
+ process $proc$ls180.v:2642$3662
assign { } { }
assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0]
end
attribute \src "ls180.v:2643.5-2643.41"
- process $proc$ls180.v:2643$3670
+ process $proc$ls180.v:2643$3663
assign { } { }
assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0]
end
attribute \src "ls180.v:2644.5-2644.41"
- process $proc$ls180.v:2644$3671
+ process $proc$ls180.v:2644$3664
assign { } { }
assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0
sync always
update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0]
end
attribute \src "ls180.v:2645.5-2645.39"
- process $proc$ls180.v:2645$3672
+ process $proc$ls180.v:2645$3665
assign { } { }
assign $1\builder_sync_f_array_muxed0[0:0] 1'0
sync always
update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0]
end
attribute \src "ls180.v:2646.5-2646.39"
- process $proc$ls180.v:2646$3673
+ process $proc$ls180.v:2646$3666
assign { } { }
assign $1\builder_sync_f_array_muxed1[0:0] 1'0
sync always
update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0]
end
attribute \src "ls180.v:267.12-267.38"
- process $proc$ls180.v:267$2834
+ process $proc$ls180.v:267$2827
assign { } { }
assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000
sync always
update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0]
end
attribute \src "ls180.v:268.5-268.36"
- process $proc$ls180.v:268$2835
+ process $proc$ls180.v:268$2828
assign { } { }
assign $1\main_dfi_p0_rddata_valid[0:0] 1'0
sync always
update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0]
end
attribute \src "ls180.v:269.11-269.32"
- process $proc$ls180.v:269$2836
+ process $proc$ls180.v:269$2829
assign { } { }
assign $1\main_rddata_en[2:0] 3'000
sync always
update \main_rddata_en $1\main_rddata_en[2:0]
end
attribute \src "ls180.v:2703.32-2703.66"
- process $proc$ls180.v:2703$3674
+ process $proc$ls180.v:2703$3667
assign { } { }
assign $1\builder_multiregimpl0_regs0[0:0] 1'0
sync always
update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0]
end
attribute \src "ls180.v:2704.32-2704.66"
- process $proc$ls180.v:2704$3675
+ process $proc$ls180.v:2704$3668
assign { } { }
assign $1\builder_multiregimpl0_regs1[0:0] 1'0
sync always
update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0]
end
attribute \src "ls180.v:2705.32-2705.66"
- process $proc$ls180.v:2705$3676
+ process $proc$ls180.v:2705$3669
assign { } { }
assign $1\builder_multiregimpl1_regs0[0:0] 1'0
sync always
update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0]
end
attribute \src "ls180.v:2706.32-2706.66"
- process $proc$ls180.v:2706$3677
+ process $proc$ls180.v:2706$3670
assign { } { }
assign $1\builder_multiregimpl1_regs1[0:0] 1'0
sync always
update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0]
end
attribute \src "ls180.v:2707.32-2707.66"
- process $proc$ls180.v:2707$3678
+ process $proc$ls180.v:2707$3671
assign { } { }
assign $1\builder_multiregimpl2_regs0[0:0] 1'0
sync always
update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0]
end
attribute \src "ls180.v:2708.32-2708.66"
- process $proc$ls180.v:2708$3679
+ process $proc$ls180.v:2708$3672
assign { } { }
assign $1\builder_multiregimpl2_regs1[0:0] 1'0
sync always
update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0]
end
attribute \src "ls180.v:2709.32-2709.66"
- process $proc$ls180.v:2709$3680
+ process $proc$ls180.v:2709$3673
assign { } { }
assign $1\builder_multiregimpl3_regs0[0:0] 1'0
sync always
update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0]
end
attribute \src "ls180.v:2710.32-2710.66"
- process $proc$ls180.v:2710$3681
+ process $proc$ls180.v:2710$3674
assign { } { }
assign $1\builder_multiregimpl3_regs1[0:0] 1'0
sync always
update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0]
end
attribute \src "ls180.v:2711.32-2711.66"
- process $proc$ls180.v:2711$3682
+ process $proc$ls180.v:2711$3675
assign { } { }
assign $1\builder_multiregimpl4_regs0[0:0] 1'0
sync always
update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0]
end
attribute \src "ls180.v:2712.32-2712.66"
- process $proc$ls180.v:2712$3683
+ process $proc$ls180.v:2712$3676
assign { } { }
assign $1\builder_multiregimpl4_regs1[0:0] 1'0
sync always
update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0]
end
attribute \src "ls180.v:2713.32-2713.66"
- process $proc$ls180.v:2713$3684
+ process $proc$ls180.v:2713$3677
assign { } { }
assign $1\builder_multiregimpl5_regs0[0:0] 1'0
sync always
update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0]
end
attribute \src "ls180.v:2714.32-2714.66"
- process $proc$ls180.v:2714$3685
+ process $proc$ls180.v:2714$3678
assign { } { }
assign $1\builder_multiregimpl5_regs1[0:0] 1'0
sync always
update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0]
end
attribute \src "ls180.v:2715.32-2715.66"
- process $proc$ls180.v:2715$3686
+ process $proc$ls180.v:2715$3679
assign { } { }
assign $1\builder_multiregimpl6_regs0[0:0] 1'0
sync always
update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0]
end
attribute \src "ls180.v:2716.32-2716.66"
- process $proc$ls180.v:2716$3687
+ process $proc$ls180.v:2716$3680
assign { } { }
assign $1\builder_multiregimpl6_regs1[0:0] 1'0
sync always
update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0]
end
attribute \src "ls180.v:2717.32-2717.66"
- process $proc$ls180.v:2717$3688
+ process $proc$ls180.v:2717$3681
assign { } { }
assign $1\builder_multiregimpl7_regs0[0:0] 1'0
sync always
update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0]
end
attribute \src "ls180.v:2718.32-2718.66"
- process $proc$ls180.v:2718$3689
+ process $proc$ls180.v:2718$3682
assign { } { }
assign $1\builder_multiregimpl7_regs1[0:0] 1'0
sync always
update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0]
end
attribute \src "ls180.v:2719.32-2719.66"
- process $proc$ls180.v:2719$3690
+ process $proc$ls180.v:2719$3683
assign { } { }
assign $1\builder_multiregimpl8_regs0[0:0] 1'0
sync always
update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0]
end
attribute \src "ls180.v:272.5-272.36"
- process $proc$ls180.v:272$2837
+ process $proc$ls180.v:272$2830
assign { } { }
assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0]
end
attribute \src "ls180.v:2720.32-2720.66"
- process $proc$ls180.v:2720$3691
+ process $proc$ls180.v:2720$3684
assign { } { }
assign $1\builder_multiregimpl8_regs1[0:0] 1'0
sync always
update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0]
end
attribute \src "ls180.v:2721.32-2721.66"
- process $proc$ls180.v:2721$3692
+ process $proc$ls180.v:2721$3685
assign { } { }
assign $1\builder_multiregimpl9_regs0[0:0] 1'0
sync always
update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0]
end
attribute \src "ls180.v:2722.32-2722.66"
- process $proc$ls180.v:2722$3693
+ process $proc$ls180.v:2722$3686
assign { } { }
assign $1\builder_multiregimpl9_regs1[0:0] 1'0
sync always
update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0]
end
attribute \src "ls180.v:2723.32-2723.67"
- process $proc$ls180.v:2723$3694
+ process $proc$ls180.v:2723$3687
assign { } { }
assign $1\builder_multiregimpl10_regs0[0:0] 1'0
sync always
update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0]
end
attribute \src "ls180.v:2724.32-2724.67"
- process $proc$ls180.v:2724$3695
+ process $proc$ls180.v:2724$3688
assign { } { }
assign $1\builder_multiregimpl10_regs1[0:0] 1'0
sync always
update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0]
end
attribute \src "ls180.v:2725.32-2725.67"
- process $proc$ls180.v:2725$3696
+ process $proc$ls180.v:2725$3689
assign { } { }
assign $1\builder_multiregimpl11_regs0[0:0] 1'0
sync always
update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0]
end
attribute \src "ls180.v:2726.32-2726.67"
- process $proc$ls180.v:2726$3697
+ process $proc$ls180.v:2726$3690
assign { } { }
assign $1\builder_multiregimpl11_regs1[0:0] 1'0
sync always
update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0]
end
attribute \src "ls180.v:2727.32-2727.67"
- process $proc$ls180.v:2727$3698
+ process $proc$ls180.v:2727$3691
assign { } { }
assign $1\builder_multiregimpl12_regs0[0:0] 1'0
sync always
update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0]
end
attribute \src "ls180.v:2728.32-2728.67"
- process $proc$ls180.v:2728$3699
+ process $proc$ls180.v:2728$3692
assign { } { }
assign $1\builder_multiregimpl12_regs1[0:0] 1'0
sync always
update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0]
end
attribute \src "ls180.v:2729.32-2729.67"
- process $proc$ls180.v:2729$3700
+ process $proc$ls180.v:2729$3693
assign { } { }
assign $1\builder_multiregimpl13_regs0[0:0] 1'0
sync always
update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0]
end
attribute \src "ls180.v:273.5-273.35"
- process $proc$ls180.v:273$2838
+ process $proc$ls180.v:273$2831
assign { } { }
assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0]
end
attribute \src "ls180.v:2730.32-2730.67"
- process $proc$ls180.v:2730$3701
+ process $proc$ls180.v:2730$3694
assign { } { }
assign $1\builder_multiregimpl13_regs1[0:0] 1'0
sync always
update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0]
end
attribute \src "ls180.v:2731.32-2731.67"
- process $proc$ls180.v:2731$3702
+ process $proc$ls180.v:2731$3695
assign { } { }
assign $1\builder_multiregimpl14_regs0[0:0] 1'0
sync always
update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0]
end
attribute \src "ls180.v:2732.32-2732.67"
- process $proc$ls180.v:2732$3703
+ process $proc$ls180.v:2732$3696
assign { } { }
assign $1\builder_multiregimpl14_regs1[0:0] 1'0
sync always
update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0]
end
attribute \src "ls180.v:2733.32-2733.67"
- process $proc$ls180.v:2733$3704
+ process $proc$ls180.v:2733$3697
assign { } { }
assign $1\builder_multiregimpl15_regs0[0:0] 1'0
sync always
update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0]
end
attribute \src "ls180.v:2734.32-2734.67"
- process $proc$ls180.v:2734$3705
+ process $proc$ls180.v:2734$3698
assign { } { }
assign $1\builder_multiregimpl15_regs1[0:0] 1'0
sync always
update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0]
end
attribute \src "ls180.v:2735.32-2735.67"
- process $proc$ls180.v:2735$3706
+ process $proc$ls180.v:2735$3699
assign { } { }
assign $1\builder_multiregimpl16_regs0[0:0] 1'0
sync always
update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0]
end
attribute \src "ls180.v:2736.32-2736.67"
- process $proc$ls180.v:2736$3707
+ process $proc$ls180.v:2736$3700
assign { } { }
assign $1\builder_multiregimpl16_regs1[0:0] 1'0
sync always
update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0]
end
attribute \src "ls180.v:274.5-274.36"
- process $proc$ls180.v:274$2839
+ process $proc$ls180.v:274$2832
assign { } { }
assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0]
end
attribute \src "ls180.v:275.5-275.35"
- process $proc$ls180.v:275$2840
+ process $proc$ls180.v:275$2833
assign { } { }
assign $1\main_sdram_inti_p0_we_n[0:0] 1'1
sync always
update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0]
end
attribute \src "ls180.v:279.5-279.36"
- process $proc$ls180.v:279$2841
+ process $proc$ls180.v:279$2834
assign { } { }
assign $0\main_sdram_inti_p0_act_n[0:0] 1'1
sync always
update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0]
end
attribute \src "ls180.v:284.12-284.45"
- process $proc$ls180.v:284$2842
+ process $proc$ls180.v:284$2835
assign { } { }
assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000
sync always
update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0]
end
attribute \src "ls180.v:285.5-285.43"
- process $proc$ls180.v:285$2843
+ process $proc$ls180.v:285$2836
assign { } { }
assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0
sync always
update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0]
end
attribute \src "ls180.v:300.12-300.46"
- process $proc$ls180.v:300$2844
+ process $proc$ls180.v:300$2837
assign { } { }
assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000
sync always
update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0]
end
attribute \src "ls180.v:301.5-301.44"
- process $proc$ls180.v:301$2845
+ process $proc$ls180.v:301$2838
assign { } { }
assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0
sync always
update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0]
end
attribute \src "ls180.v:302.12-302.48"
- process $proc$ls180.v:302$2846
+ process $proc$ls180.v:302$2839
assign { } { }
assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000
sync always
update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0]
end
attribute \src "ls180.v:303.11-303.43"
- process $proc$ls180.v:303$2847
+ process $proc$ls180.v:303$2840
assign { } { }
assign $1\main_sdram_master_p0_bank[1:0] 2'00
sync always
update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0]
end
attribute \src "ls180.v:304.5-304.38"
- process $proc$ls180.v:304$2848
+ process $proc$ls180.v:304$2841
assign { } { }
assign $1\main_sdram_master_p0_cas_n[0:0] 1'1
sync always
update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0]
end
attribute \src "ls180.v:305.5-305.37"
- process $proc$ls180.v:305$2849
+ process $proc$ls180.v:305$2842
assign { } { }
assign $1\main_sdram_master_p0_cs_n[0:0] 1'1
sync always
update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0]
end
attribute \src "ls180.v:306.5-306.38"
- process $proc$ls180.v:306$2850
+ process $proc$ls180.v:306$2843
assign { } { }
assign $1\main_sdram_master_p0_ras_n[0:0] 1'1
sync always
update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0]
end
attribute \src "ls180.v:307.5-307.37"
- process $proc$ls180.v:307$2851
+ process $proc$ls180.v:307$2844
assign { } { }
assign $1\main_sdram_master_p0_we_n[0:0] 1'1
sync always
update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0]
end
attribute \src "ls180.v:308.5-308.36"
- process $proc$ls180.v:308$2852
+ process $proc$ls180.v:308$2845
assign { } { }
assign $1\main_sdram_master_p0_cke[0:0] 1'0
sync always
update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0]
end
attribute \src "ls180.v:309.5-309.36"
- process $proc$ls180.v:309$2853
+ process $proc$ls180.v:309$2846
assign { } { }
assign $1\main_sdram_master_p0_odt[0:0] 1'0
sync always
update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0]
end
attribute \src "ls180.v:310.5-310.40"
- process $proc$ls180.v:310$2854
+ process $proc$ls180.v:310$2847
assign { } { }
assign $1\main_sdram_master_p0_reset_n[0:0] 1'0
sync always
update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0]
end
attribute \src "ls180.v:311.5-311.38"
- process $proc$ls180.v:311$2855
+ process $proc$ls180.v:311$2848
assign { } { }
assign $1\main_sdram_master_p0_act_n[0:0] 1'1
sync always
update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0]
end
attribute \src "ls180.v:312.12-312.47"
- process $proc$ls180.v:312$2856
+ process $proc$ls180.v:312$2849
assign { } { }
assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000
sync always
update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0]
end
attribute \src "ls180.v:313.5-313.42"
- process $proc$ls180.v:313$2857
+ process $proc$ls180.v:313$2850
assign { } { }
assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0
sync always
update \builder_refresher_next_state $0\builder_refresher_next_state[1:0]
end
attribute \src "ls180.v:314.11-314.50"
- process $proc$ls180.v:314$2858
+ process $proc$ls180.v:314$2851
assign { } { }
assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00
sync always
update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0]
end
attribute \src "ls180.v:315.5-315.42"
- process $proc$ls180.v:315$2859
+ process $proc$ls180.v:315$2852
assign { } { }
assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:322.11-322.36"
- process $proc$ls180.v:322$2860
+ process $proc$ls180.v:322$2853
assign { } { }
assign $1\main_sdram_storage[3:0] 4'0001
sync always
update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0]
end
attribute \src "ls180.v:323.5-323.25"
- process $proc$ls180.v:323$2861
+ process $proc$ls180.v:323$2854
assign { } { }
assign $1\main_sdram_re[0:0] 1'0
sync always
update \main_sdram_re $1\main_sdram_re[0:0]
end
attribute \src "ls180.v:324.11-324.44"
- process $proc$ls180.v:324$2862
+ process $proc$ls180.v:324$2855
assign { } { }
assign $1\main_sdram_command_storage[5:0] 6'000000
sync always
update \main_sdram_command_storage $1\main_sdram_command_storage[5:0]
end
attribute \src "ls180.v:325.5-325.33"
- process $proc$ls180.v:325$2863
+ process $proc$ls180.v:325$2856
assign { } { }
assign $1\main_sdram_command_re[0:0] 1'0
sync always
update \main_sdram_command_re $1\main_sdram_command_re[0:0]
end
attribute \src "ls180.v:329.5-329.38"
- process $proc$ls180.v:329$2864
+ process $proc$ls180.v:329$2857
assign { } { }
assign $0\main_sdram_command_issue_w[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:330.12-330.46"
- process $proc$ls180.v:330$2865
+ process $proc$ls180.v:330$2858
assign { } { }
assign $1\main_sdram_address_storage[12:0] 13'0000000000000
sync always
update \main_sdram_address_storage $1\main_sdram_address_storage[12:0]
end
attribute \src "ls180.v:331.5-331.33"
- process $proc$ls180.v:331$2866
+ process $proc$ls180.v:331$2859
assign { } { }
assign $1\main_sdram_address_re[0:0] 1'0
sync always
update \main_sdram_address_re $1\main_sdram_address_re[0:0]
end
attribute \src "ls180.v:332.11-332.45"
- process $proc$ls180.v:332$2867
+ process $proc$ls180.v:332$2860
assign { } { }
assign $1\main_sdram_baddress_storage[1:0] 2'00
sync always
update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0]
end
attribute \src "ls180.v:333.5-333.34"
- process $proc$ls180.v:333$2868
+ process $proc$ls180.v:333$2861
assign { } { }
assign $1\main_sdram_baddress_re[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0]
end
attribute \src "ls180.v:334.12-334.45"
- process $proc$ls180.v:334$2869
+ process $proc$ls180.v:334$2862
assign { } { }
assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000
sync always
update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0]
end
attribute \src "ls180.v:335.5-335.32"
- process $proc$ls180.v:335$2870
+ process $proc$ls180.v:335$2863
assign { } { }
assign $1\main_sdram_wrdata_re[0:0] 1'0
sync always
update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0]
end
attribute \src "ls180.v:336.12-336.37"
- process $proc$ls180.v:336$2871
+ process $proc$ls180.v:336$2864
assign { } { }
assign $1\main_sdram_status[15:0] 16'0000000000000000
sync always
update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0]
end
attribute \src "ls180.v:366.12-366.46"
- process $proc$ls180.v:366$2872
+ process $proc$ls180.v:366$2865
assign { } { }
assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000
sync always
update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0]
end
attribute \src "ls180.v:367.11-367.47"
- process $proc$ls180.v:367$2873
+ process $proc$ls180.v:367$2866
assign { } { }
assign $1\main_sdram_interface_wdata_we[1:0] 2'00
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0]
end
attribute \src "ls180.v:369.12-369.45"
- process $proc$ls180.v:369$2874
+ process $proc$ls180.v:369$2867
assign { } { }
assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000
sync always
update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0]
end
attribute \src "ls180.v:370.11-370.40"
- process $proc$ls180.v:370$2875
+ process $proc$ls180.v:370$2868
assign { } { }
assign $1\main_sdram_dfi_p0_bank[1:0] 2'00
sync always
update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0]
end
attribute \src "ls180.v:371.5-371.35"
- process $proc$ls180.v:371$2876
+ process $proc$ls180.v:371$2869
assign { } { }
assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1
sync always
update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0]
end
attribute \src "ls180.v:372.5-372.34"
- process $proc$ls180.v:372$2877
+ process $proc$ls180.v:372$2870
assign { } { }
assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1
sync always
update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0]
end
attribute \src "ls180.v:373.5-373.35"
- process $proc$ls180.v:373$2878
+ process $proc$ls180.v:373$2871
assign { } { }
assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1
sync always
update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0]
end
attribute \src "ls180.v:374.5-374.34"
- process $proc$ls180.v:374$2879
+ process $proc$ls180.v:374$2872
assign { } { }
assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1
sync always
update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0]
end
attribute \src "ls180.v:378.5-378.35"
- process $proc$ls180.v:378$2880
+ process $proc$ls180.v:378$2873
assign { } { }
assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:380.5-380.39"
- process $proc$ls180.v:380$2881
+ process $proc$ls180.v:380$2874
assign { } { }
assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0
sync always
update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0]
end
attribute \src "ls180.v:382.5-382.39"
- process $proc$ls180.v:382$2882
+ process $proc$ls180.v:382$2875
assign { } { }
assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0
sync always
update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0]
end
attribute \src "ls180.v:385.5-385.32"
- process $proc$ls180.v:385$2883
+ process $proc$ls180.v:385$2876
assign { } { }
assign $1\main_sdram_cmd_valid[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:386.5-386.32"
- process $proc$ls180.v:386$2884
+ process $proc$ls180.v:386$2877
assign { } { }
assign $1\main_sdram_cmd_ready[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0]
end
attribute \src "ls180.v:387.5-387.31"
- process $proc$ls180.v:387$2885
+ process $proc$ls180.v:387$2878
assign { } { }
assign $1\main_sdram_cmd_last[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0]
end
attribute \src "ls180.v:388.12-388.44"
- process $proc$ls180.v:388$2886
+ process $proc$ls180.v:388$2879
assign { } { }
assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0]
end
attribute \src "ls180.v:389.11-389.43"
- process $proc$ls180.v:389$2887
+ process $proc$ls180.v:389$2880
assign { } { }
assign $1\main_sdram_cmd_payload_ba[1:0] 2'00
sync always
update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0]
end
attribute \src "ls180.v:390.5-390.38"
- process $proc$ls180.v:390$2888
+ process $proc$ls180.v:390$2881
assign { } { }
assign $1\main_sdram_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0]
end
attribute \src "ls180.v:391.5-391.38"
- process $proc$ls180.v:391$2889
+ process $proc$ls180.v:391$2882
assign { } { }
assign $1\main_sdram_cmd_payload_ras[0:0] 1'0
sync always
update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0]
end
attribute \src "ls180.v:392.5-392.37"
- process $proc$ls180.v:392$2890
+ process $proc$ls180.v:392$2883
assign { } { }
assign $1\main_sdram_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0]
end
attribute \src "ls180.v:393.5-393.42"
- process $proc$ls180.v:393$2891
+ process $proc$ls180.v:393$2884
assign { } { }
assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:394.5-394.43"
- process $proc$ls180.v:394$2892
+ process $proc$ls180.v:394$2885
assign { } { }
assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:400.11-400.44"
- process $proc$ls180.v:400$2893
+ process $proc$ls180.v:400$2886
assign { } { }
assign $1\main_sdram_timer_count1[9:0] 10'1100001101
sync always
update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0]
end
attribute \src "ls180.v:402.5-402.38"
- process $proc$ls180.v:402$2894
+ process $proc$ls180.v:402$2887
assign { } { }
assign $1\main_sdram_postponer_req_o[0:0] 1'0
sync always
update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0]
end
attribute \src "ls180.v:403.5-403.38"
- process $proc$ls180.v:403$2895
+ process $proc$ls180.v:403$2888
assign { } { }
assign $1\main_sdram_postponer_count[0:0] 1'0
sync always
update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0]
end
attribute \src "ls180.v:404.5-404.39"
- process $proc$ls180.v:404$2896
+ process $proc$ls180.v:404$2889
assign { } { }
assign $1\main_sdram_sequencer_start0[0:0] 1'0
sync always
update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0]
end
attribute \src "ls180.v:407.5-407.38"
- process $proc$ls180.v:407$2897
+ process $proc$ls180.v:407$2890
assign { } { }
assign $1\main_sdram_sequencer_done1[0:0] 1'0
sync always
update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0]
end
attribute \src "ls180.v:408.11-408.46"
- process $proc$ls180.v:408$2898
+ process $proc$ls180.v:408$2891
assign { } { }
assign $1\main_sdram_sequencer_counter[3:0] 4'0000
sync always
update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0]
end
attribute \src "ls180.v:409.5-409.38"
- process $proc$ls180.v:409$2899
+ process $proc$ls180.v:409$2892
assign { } { }
assign $1\main_sdram_sequencer_count[0:0] 1'0
sync always
update \main_uart_rx_clear $0\main_uart_rx_clear[0:0]
end
attribute \src "ls180.v:415.5-415.51"
- process $proc$ls180.v:415$2900
+ process $proc$ls180.v:415$2893
assign { } { }
assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0
sync always
update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0]
end
attribute \src "ls180.v:416.5-416.51"
- process $proc$ls180.v:416$2901
+ process $proc$ls180.v:416$2894
assign { } { }
assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0
sync always
update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0]
end
attribute \src "ls180.v:418.5-418.47"
- process $proc$ls180.v:418$2902
+ process $proc$ls180.v:418$2895
assign { } { }
assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0]
end
attribute \src "ls180.v:419.5-419.45"
- process $proc$ls180.v:419$2903
+ process $proc$ls180.v:419$2896
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0]
end
attribute \src "ls180.v:420.5-420.45"
- process $proc$ls180.v:420$2904
+ process $proc$ls180.v:420$2897
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0
sync always
update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0]
end
attribute \src "ls180.v:421.12-421.57"
- process $proc$ls180.v:421$2905
+ process $proc$ls180.v:421$2898
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0]
end
attribute \src "ls180.v:423.5-423.51"
- process $proc$ls180.v:423$2906
+ process $proc$ls180.v:423$2899
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0
sync always
update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0]
end
attribute \src "ls180.v:424.5-424.51"
- process $proc$ls180.v:424$2907
+ process $proc$ls180.v:424$2900
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:425.5-425.50"
- process $proc$ls180.v:425$2908
+ process $proc$ls180.v:425$2901
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0]
end
attribute \src "ls180.v:426.5-426.54"
- process $proc$ls180.v:426$2909
+ process $proc$ls180.v:426$2902
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0]
end
attribute \src "ls180.v:427.5-427.55"
- process $proc$ls180.v:427$2910
+ process $proc$ls180.v:427$2903
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:428.5-428.56"
- process $proc$ls180.v:428$2911
+ process $proc$ls180.v:428$2904
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0]
end
attribute \src "ls180.v:429.5-429.50"
- process $proc$ls180.v:429$2912
+ process $proc$ls180.v:429$2905
assign { } { }
assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0
sync always
update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0]
end
attribute \src "ls180.v:432.5-432.67"
- process $proc$ls180.v:432$2913
+ process $proc$ls180.v:432$2906
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:433.5-433.66"
- process $proc$ls180.v:433$2914
+ process $proc$ls180.v:433$2907
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0]
end
attribute \src "ls180.v:448.11-448.68"
- process $proc$ls180.v:448$2915
+ process $proc$ls180.v:448$2908
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0]
end
attribute \src "ls180.v:449.5-449.64"
- process $proc$ls180.v:449$2916
+ process $proc$ls180.v:449$2909
assign { } { }
assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:450.11-450.70"
- process $proc$ls180.v:450$2917
+ process $proc$ls180.v:450$2910
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0]
end
attribute \src "ls180.v:451.11-451.70"
- process $proc$ls180.v:451$2918
+ process $proc$ls180.v:451$2911
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0]
end
attribute \src "ls180.v:452.11-452.73"
- process $proc$ls180.v:452$2919
+ process $proc$ls180.v:452$2912
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:473.5-473.59"
- process $proc$ls180.v:473$2920
+ process $proc$ls180.v:473$2913
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0]
end
attribute \src "ls180.v:475.5-475.59"
- process $proc$ls180.v:475$2921
+ process $proc$ls180.v:475$2914
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:476.5-476.58"
- process $proc$ls180.v:476$2922
+ process $proc$ls180.v:476$2915
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:477.5-477.64"
- process $proc$ls180.v:477$2923
+ process $proc$ls180.v:477$2916
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0]
end
attribute \src "ls180.v:478.12-478.74"
- process $proc$ls180.v:478$2924
+ process $proc$ls180.v:478$2917
assign { } { }
assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0]
end
attribute \src "ls180.v:479.12-479.47"
- process $proc$ls180.v:479$2925
+ process $proc$ls180.v:479$2918
assign { } { }
assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0]
end
attribute \src "ls180.v:480.5-480.46"
- process $proc$ls180.v:480$2926
+ process $proc$ls180.v:480$2919
assign { } { }
assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0
sync always
update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0]
end
attribute \src "ls180.v:482.5-482.44"
- process $proc$ls180.v:482$2927
+ process $proc$ls180.v:482$2920
assign { } { }
assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0
sync always
update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0]
end
attribute \src "ls180.v:483.5-483.45"
- process $proc$ls180.v:483$2928
+ process $proc$ls180.v:483$2921
assign { } { }
assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0]
end
attribute \src "ls180.v:484.5-484.54"
- process $proc$ls180.v:484$2929
+ process $proc$ls180.v:484$2922
assign { } { }
assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0]
end
attribute \src "ls180.v:486.32-486.76"
- process $proc$ls180.v:486$2930
+ process $proc$ls180.v:486$2923
assign { } { }
assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0]
end
attribute \src "ls180.v:487.11-487.55"
- process $proc$ls180.v:487$2931
+ process $proc$ls180.v:487$2924
assign { } { }
assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000
sync always
update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0]
end
attribute \src "ls180.v:489.32-489.75"
- process $proc$ls180.v:489$2932
+ process $proc$ls180.v:489$2925
assign { } { }
assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:491.32-491.76"
- process $proc$ls180.v:491$2933
+ process $proc$ls180.v:491$2926
assign { } { }
assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1
sync always
update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0]
end
attribute \src "ls180.v:497.5-497.51"
- process $proc$ls180.v:497$2934
+ process $proc$ls180.v:497$2927
assign { } { }
assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0]
end
attribute \src "ls180.v:498.5-498.51"
- process $proc$ls180.v:498$2935
+ process $proc$ls180.v:498$2928
assign { } { }
assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
attribute \src "ls180.v:500.5-500.47"
- process $proc$ls180.v:500$2936
+ process $proc$ls180.v:500$2929
assign { } { }
assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0]
end
attribute \src "ls180.v:501.5-501.45"
- process $proc$ls180.v:501$2937
+ process $proc$ls180.v:501$2930
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0]
end
attribute \src "ls180.v:502.5-502.45"
- process $proc$ls180.v:502$2938
+ process $proc$ls180.v:502$2931
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0
sync always
update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0]
end
attribute \src "ls180.v:503.12-503.57"
- process $proc$ls180.v:503$2939
+ process $proc$ls180.v:503$2932
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0]
end
attribute \src "ls180.v:505.5-505.51"
- process $proc$ls180.v:505$2940
+ process $proc$ls180.v:505$2933
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:506.5-506.51"
- process $proc$ls180.v:506$2941
+ process $proc$ls180.v:506$2934
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:507.5-507.50"
- process $proc$ls180.v:507$2942
+ process $proc$ls180.v:507$2935
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0]
end
attribute \src "ls180.v:508.5-508.54"
- process $proc$ls180.v:508$2943
+ process $proc$ls180.v:508$2936
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0]
end
attribute \src "ls180.v:509.5-509.55"
- process $proc$ls180.v:509$2944
+ process $proc$ls180.v:509$2937
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:510.5-510.56"
- process $proc$ls180.v:510$2945
+ process $proc$ls180.v:510$2938
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0]
end
attribute \src "ls180.v:511.5-511.50"
- process $proc$ls180.v:511$2946
+ process $proc$ls180.v:511$2939
assign { } { }
assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0]
end
attribute \src "ls180.v:514.5-514.67"
- process $proc$ls180.v:514$2947
+ process $proc$ls180.v:514$2940
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0]
end
attribute \src "ls180.v:515.5-515.66"
- process $proc$ls180.v:515$2948
+ process $proc$ls180.v:515$2941
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0]
end
attribute \src "ls180.v:530.11-530.68"
- process $proc$ls180.v:530$2949
+ process $proc$ls180.v:530$2942
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0]
end
attribute \src "ls180.v:531.5-531.64"
- process $proc$ls180.v:531$2950
+ process $proc$ls180.v:531$2943
assign { } { }
assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:532.11-532.70"
- process $proc$ls180.v:532$2951
+ process $proc$ls180.v:532$2944
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0]
end
attribute \src "ls180.v:533.11-533.70"
- process $proc$ls180.v:533$2952
+ process $proc$ls180.v:533$2945
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0]
end
attribute \src "ls180.v:534.11-534.73"
- process $proc$ls180.v:534$2953
+ process $proc$ls180.v:534$2946
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0]
end
attribute \src "ls180.v:555.5-555.59"
- process $proc$ls180.v:555$2954
+ process $proc$ls180.v:555$2947
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0
sync always
update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0]
end
attribute \src "ls180.v:557.5-557.59"
- process $proc$ls180.v:557$2955
+ process $proc$ls180.v:557$2948
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:558.5-558.58"
- process $proc$ls180.v:558$2956
+ process $proc$ls180.v:558$2949
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:559.5-559.64"
- process $proc$ls180.v:559$2957
+ process $proc$ls180.v:559$2950
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0]
end
attribute \src "ls180.v:560.12-560.74"
- process $proc$ls180.v:560$2958
+ process $proc$ls180.v:560$2951
assign { } { }
assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0]
end
attribute \src "ls180.v:561.12-561.47"
- process $proc$ls180.v:561$2959
+ process $proc$ls180.v:561$2952
assign { } { }
assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0]
end
attribute \src "ls180.v:562.5-562.46"
- process $proc$ls180.v:562$2960
+ process $proc$ls180.v:562$2953
assign { } { }
assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0
sync always
update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0]
end
attribute \src "ls180.v:564.5-564.44"
- process $proc$ls180.v:564$2961
+ process $proc$ls180.v:564$2954
assign { } { }
assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0
sync always
update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0]
end
attribute \src "ls180.v:565.5-565.45"
- process $proc$ls180.v:565$2962
+ process $proc$ls180.v:565$2955
assign { } { }
assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0]
end
attribute \src "ls180.v:566.5-566.54"
- process $proc$ls180.v:566$2963
+ process $proc$ls180.v:566$2956
assign { } { }
assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0]
end
attribute \src "ls180.v:568.32-568.76"
- process $proc$ls180.v:568$2964
+ process $proc$ls180.v:568$2957
assign { } { }
assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0]
end
attribute \src "ls180.v:569.11-569.55"
- process $proc$ls180.v:569$2965
+ process $proc$ls180.v:569$2958
assign { } { }
assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000
sync always
update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0]
end
attribute \src "ls180.v:571.32-571.75"
- process $proc$ls180.v:571$2966
+ process $proc$ls180.v:571$2959
assign { } { }
assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1
sync always
update \builder_slave_sel $0\builder_slave_sel[4:0]
end
attribute \src "ls180.v:573.32-573.76"
- process $proc$ls180.v:573$2967
+ process $proc$ls180.v:573$2960
assign { } { }
assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1
sync always
update \builder_error $0\builder_error[0:0]
end
attribute \src "ls180.v:579.5-579.51"
- process $proc$ls180.v:579$2968
+ process $proc$ls180.v:579$2961
assign { } { }
assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0
sync always
update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0]
end
attribute \src "ls180.v:580.5-580.51"
- process $proc$ls180.v:580$2969
+ process $proc$ls180.v:580$2962
assign { } { }
assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0]
end
attribute \src "ls180.v:582.5-582.47"
- process $proc$ls180.v:582$2970
+ process $proc$ls180.v:582$2963
assign { } { }
assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0]
end
attribute \src "ls180.v:583.5-583.45"
- process $proc$ls180.v:583$2971
+ process $proc$ls180.v:583$2964
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0]
end
attribute \src "ls180.v:584.5-584.45"
- process $proc$ls180.v:584$2972
+ process $proc$ls180.v:584$2965
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0]
end
attribute \src "ls180.v:585.12-585.57"
- process $proc$ls180.v:585$2973
+ process $proc$ls180.v:585$2966
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0]
end
attribute \src "ls180.v:587.5-587.51"
- process $proc$ls180.v:587$2974
+ process $proc$ls180.v:587$2967
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:588.5-588.51"
- process $proc$ls180.v:588$2975
+ process $proc$ls180.v:588$2968
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:589.5-589.50"
- process $proc$ls180.v:589$2976
+ process $proc$ls180.v:589$2969
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0]
end
attribute \src "ls180.v:590.5-590.54"
- process $proc$ls180.v:590$2977
+ process $proc$ls180.v:590$2970
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0]
end
attribute \src "ls180.v:591.5-591.55"
- process $proc$ls180.v:591$2978
+ process $proc$ls180.v:591$2971
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:592.5-592.56"
- process $proc$ls180.v:592$2979
+ process $proc$ls180.v:592$2972
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0]
end
attribute \src "ls180.v:593.5-593.50"
- process $proc$ls180.v:593$2980
+ process $proc$ls180.v:593$2973
assign { } { }
assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0
sync always
update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0]
end
attribute \src "ls180.v:596.5-596.67"
- process $proc$ls180.v:596$2981
+ process $proc$ls180.v:596$2974
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:597.5-597.66"
- process $proc$ls180.v:597$2982
+ process $proc$ls180.v:597$2975
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:612.11-612.68"
- process $proc$ls180.v:612$2983
+ process $proc$ls180.v:612$2976
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0]
end
attribute \src "ls180.v:613.5-613.64"
- process $proc$ls180.v:613$2984
+ process $proc$ls180.v:613$2977
assign { } { }
assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:614.11-614.70"
- process $proc$ls180.v:614$2985
+ process $proc$ls180.v:614$2978
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0]
end
attribute \src "ls180.v:615.11-615.70"
- process $proc$ls180.v:615$2986
+ process $proc$ls180.v:615$2979
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0]
end
attribute \src "ls180.v:616.11-616.73"
- process $proc$ls180.v:616$2987
+ process $proc$ls180.v:616$2980
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0]
end
attribute \src "ls180.v:637.5-637.59"
- process $proc$ls180.v:637$2988
+ process $proc$ls180.v:637$2981
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0]
end
attribute \src "ls180.v:639.5-639.59"
- process $proc$ls180.v:639$2989
+ process $proc$ls180.v:639$2982
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:640.5-640.58"
- process $proc$ls180.v:640$2990
+ process $proc$ls180.v:640$2983
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:641.5-641.64"
- process $proc$ls180.v:641$2991
+ process $proc$ls180.v:641$2984
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0]
end
attribute \src "ls180.v:642.12-642.74"
- process $proc$ls180.v:642$2992
+ process $proc$ls180.v:642$2985
assign { } { }
assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0]
end
attribute \src "ls180.v:643.12-643.47"
- process $proc$ls180.v:643$2993
+ process $proc$ls180.v:643$2986
assign { } { }
assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0]
end
attribute \src "ls180.v:644.5-644.46"
- process $proc$ls180.v:644$2994
+ process $proc$ls180.v:644$2987
assign { } { }
assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0
sync always
update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0]
end
attribute \src "ls180.v:646.5-646.44"
- process $proc$ls180.v:646$2995
+ process $proc$ls180.v:646$2988
assign { } { }
assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0
sync always
update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0]
end
attribute \src "ls180.v:647.5-647.45"
- process $proc$ls180.v:647$2996
+ process $proc$ls180.v:647$2989
assign { } { }
assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0]
end
attribute \src "ls180.v:648.5-648.54"
- process $proc$ls180.v:648$2997
+ process $proc$ls180.v:648$2990
assign { } { }
assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0]
end
attribute \src "ls180.v:650.32-650.76"
- process $proc$ls180.v:650$2998
+ process $proc$ls180.v:650$2991
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0]
end
attribute \src "ls180.v:651.11-651.55"
- process $proc$ls180.v:651$2999
+ process $proc$ls180.v:651$2992
assign { } { }
assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000
sync always
update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0]
end
attribute \src "ls180.v:653.32-653.75"
- process $proc$ls180.v:653$3000
+ process $proc$ls180.v:653$2993
assign { } { }
assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1
sync always
update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0]
end
attribute \src "ls180.v:655.32-655.76"
- process $proc$ls180.v:655$3001
+ process $proc$ls180.v:655$2994
assign { } { }
assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1
sync always
update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0]
end
attribute \src "ls180.v:661.5-661.51"
- process $proc$ls180.v:661$3002
+ process $proc$ls180.v:661$2995
assign { } { }
assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0]
end
attribute \src "ls180.v:662.5-662.51"
- process $proc$ls180.v:662$3003
+ process $proc$ls180.v:662$2996
assign { } { }
assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0
sync always
update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0]
end
attribute \src "ls180.v:664.5-664.47"
- process $proc$ls180.v:664$3004
+ process $proc$ls180.v:664$2997
assign { } { }
assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0
sync always
update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0]
end
attribute \src "ls180.v:665.5-665.45"
- process $proc$ls180.v:665$3005
+ process $proc$ls180.v:665$2998
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0
sync always
update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0]
end
attribute \src "ls180.v:666.5-666.45"
- process $proc$ls180.v:666$3006
+ process $proc$ls180.v:666$2999
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0]
end
attribute \src "ls180.v:667.12-667.57"
- process $proc$ls180.v:667$3007
+ process $proc$ls180.v:667$3000
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000
sync always
update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0]
end
attribute \src "ls180.v:669.5-669.51"
- process $proc$ls180.v:669$3008
+ process $proc$ls180.v:669$3001
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0]
end
attribute \src "ls180.v:670.5-670.51"
- process $proc$ls180.v:670$3009
+ process $proc$ls180.v:670$3002
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0]
end
attribute \src "ls180.v:671.5-671.50"
- process $proc$ls180.v:671$3010
+ process $proc$ls180.v:671$3003
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0]
end
attribute \src "ls180.v:672.5-672.54"
- process $proc$ls180.v:672$3011
+ process $proc$ls180.v:672$3004
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0]
end
attribute \src "ls180.v:673.5-673.55"
- process $proc$ls180.v:673$3012
+ process $proc$ls180.v:673$3005
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0]
end
attribute \src "ls180.v:674.5-674.56"
- process $proc$ls180.v:674$3013
+ process $proc$ls180.v:674$3006
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0]
end
attribute \src "ls180.v:675.5-675.50"
- process $proc$ls180.v:675$3014
+ process $proc$ls180.v:675$3007
assign { } { }
assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0
sync always
update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0]
end
attribute \src "ls180.v:678.5-678.67"
- process $proc$ls180.v:678$3015
+ process $proc$ls180.v:678$3008
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:679.5-679.66"
- process $proc$ls180.v:679$3016
+ process $proc$ls180.v:679$3009
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0
sync always
update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0]
end
attribute \src "ls180.v:694.11-694.68"
- process $proc$ls180.v:694$3017
+ process $proc$ls180.v:694$3010
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000
sync always
update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0]
end
attribute \src "ls180.v:695.5-695.64"
- process $proc$ls180.v:695$3018
+ process $proc$ls180.v:695$3011
assign { } { }
assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:696.11-696.70"
- process $proc$ls180.v:696$3019
+ process $proc$ls180.v:696$3012
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000
sync always
update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0]
end
attribute \src "ls180.v:697.11-697.70"
- process $proc$ls180.v:697$3020
+ process $proc$ls180.v:697$3013
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000
sync always
update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0]
end
attribute \src "ls180.v:698.11-698.73"
- process $proc$ls180.v:698$3021
+ process $proc$ls180.v:698$3014
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000
sync always
update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0]
end
attribute \src "ls180.v:719.5-719.59"
- process $proc$ls180.v:719$3022
+ process $proc$ls180.v:719$3015
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0
sync always
update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0]
end
attribute \src "ls180.v:721.5-721.59"
- process $proc$ls180.v:721$3023
+ process $proc$ls180.v:721$3016
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0]
end
attribute \src "ls180.v:722.5-722.58"
- process $proc$ls180.v:722$3024
+ process $proc$ls180.v:722$3017
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0]
end
attribute \src "ls180.v:723.5-723.64"
- process $proc$ls180.v:723$3025
+ process $proc$ls180.v:723$3018
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0
sync always
update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0]
end
attribute \src "ls180.v:724.12-724.74"
- process $proc$ls180.v:724$3026
+ process $proc$ls180.v:724$3019
assign { } { }
assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000
sync always
update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0]
end
attribute \src "ls180.v:725.12-725.47"
- process $proc$ls180.v:725$3027
+ process $proc$ls180.v:725$3020
assign { } { }
assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000
sync always
update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0]
end
attribute \src "ls180.v:726.5-726.46"
- process $proc$ls180.v:726$3028
+ process $proc$ls180.v:726$3021
assign { } { }
assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0]
end
attribute \src "ls180.v:728.5-728.44"
- process $proc$ls180.v:728$3029
+ process $proc$ls180.v:728$3022
assign { } { }
assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0]
end
attribute \src "ls180.v:729.5-729.45"
- process $proc$ls180.v:729$3030
+ process $proc$ls180.v:729$3023
assign { } { }
assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0
sync always
update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0]
end
attribute \src "ls180.v:730.5-730.54"
- process $proc$ls180.v:730$3031
+ process $proc$ls180.v:730$3024
assign { } { }
assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0
sync always
update \main_gpio_status $0\main_gpio_status[15:0]
end
attribute \src "ls180.v:732.32-732.76"
- process $proc$ls180.v:732$3032
+ process $proc$ls180.v:732$3025
assign { } { }
assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0
sync always
update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0]
end
attribute \src "ls180.v:733.11-733.55"
- process $proc$ls180.v:733$3033
+ process $proc$ls180.v:733$3026
assign { } { }
assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000
sync always
update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0]
end
attribute \src "ls180.v:735.32-735.75"
- process $proc$ls180.v:735$3034
+ process $proc$ls180.v:735$3027
assign { } { }
assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1
sync always
update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
end
attribute \src "ls180.v:737.32-737.76"
- process $proc$ls180.v:737$3035
+ process $proc$ls180.v:737$3028
assign { } { }
assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:740.5-740.44"
- process $proc$ls180.v:740$3036
+ process $proc$ls180.v:740$3029
assign { } { }
assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:741.5-741.45"
- process $proc$ls180.v:741$3037
+ process $proc$ls180.v:741$3030
assign { } { }
assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:742.5-742.43"
- process $proc$ls180.v:742$3038
+ process $proc$ls180.v:742$3031
assign { } { }
assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:743.5-743.48"
- process $proc$ls180.v:743$3039
+ process $proc$ls180.v:743$3032
assign { } { }
assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0
sync always
end
attribute \src "ls180.v:7431.1-10043.4"
process $proc$ls180.v:7431$2374
- assign $0\spisdcard_clk[0:0] \spisdcard_clk
- assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
- assign { } { }
- assign $0\uart_tx[0:0] \uart_tx
assign $0\pwm[1:0] \pwm
+ assign $0\uart_tx[0:0] \uart_tx
assign $0\spimaster_clk[0:0] \spimaster_clk
assign $0\spimaster_mosi[0:0] \spimaster_mosi
assign { } { }
+ assign $0\spisdcard_clk[0:0] \spisdcard_clk
+ assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
+ assign { } { }
assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
assign { } { }
assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
assign $0\main_libresocsim_scratch_storage[31:0] 305419896
assign $0\main_libresocsim_scratch_re[0:0] 1'0
assign $0\main_libresocsim_bus_errors[31:0] 0
- assign $0\spisdcard_clk[0:0] 1'0
- assign $0\spisdcard_mosi[0:0] 1'0
- assign $0\spisdcard_cs_n[0:0] 1'0
- assign $0\uart_tx[0:0] 1'1
assign $0\pwm[1:0] 2'00
+ assign $0\uart_tx[0:0] 1'1
assign $0\spimaster_clk[0:0] 1'0
assign $0\spimaster_mosi[0:0] 1'0
assign $0\spimaster_cs_n[0:0] 1'0
+ assign $0\spisdcard_clk[0:0] 1'0
+ assign $0\spisdcard_mosi[0:0] 1'0
+ assign $0\spisdcard_cs_n[0:0] 1'0
assign $0\main_libresocsim_converter0_counter[0:0] 1'0
assign $0\main_libresocsim_converter1_counter[0:0] 1'0
assign $0\main_libresocsim_converter2_counter[0:0] 1'0
case
end
sync posedge \sys_clk_1
- update \spisdcard_clk $0\spisdcard_clk[0:0]
- update \spisdcard_mosi $0\spisdcard_mosi[0:0]
- update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
- update \uart_tx $0\uart_tx[0:0]
update \pwm $0\pwm[1:0]
+ update \uart_tx $0\uart_tx[0:0]
update \spimaster_clk $0\spimaster_clk[0:0]
update \spimaster_mosi $0\spimaster_mosi[0:0]
update \spimaster_cs_n $0\spimaster_cs_n[0:0]
+ update \spisdcard_clk $0\spisdcard_clk[0:0]
+ update \spisdcard_mosi $0\spisdcard_mosi[0:0]
+ update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0]
end
attribute \src "ls180.v:745.5-745.43"
- process $proc$ls180.v:745$3040
+ process $proc$ls180.v:745$3033
assign { } { }
assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:748.5-748.49"
- process $proc$ls180.v:748$3041
+ process $proc$ls180.v:748$3034
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:749.5-749.49"
- process $proc$ls180.v:749$3042
+ process $proc$ls180.v:749$3035
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:750.5-750.48"
- process $proc$ls180.v:750$3043
+ process $proc$ls180.v:750$3036
assign { } { }
assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0]
end
attribute \src "ls180.v:754.11-754.46"
- process $proc$ls180.v:754$3044
+ process $proc$ls180.v:754$3037
assign { } { }
assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000
sync always
update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0]
end
attribute \src "ls180.v:756.11-756.45"
- process $proc$ls180.v:756$3045
+ process $proc$ls180.v:756$3038
assign { } { }
assign $1\main_sdram_choose_cmd_grant[1:0] 2'00
sync always
update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0]
end
attribute \src "ls180.v:758.5-758.44"
- process $proc$ls180.v:758$3046
+ process $proc$ls180.v:758$3039
assign { } { }
assign $1\main_sdram_choose_req_want_reads[0:0] 1'0
sync always
update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0]
end
attribute \src "ls180.v:759.5-759.45"
- process $proc$ls180.v:759$3047
+ process $proc$ls180.v:759$3040
assign { } { }
assign $1\main_sdram_choose_req_want_writes[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:761.5-761.48"
- process $proc$ls180.v:761$3048
+ process $proc$ls180.v:761$3041
assign { } { }
assign $1\main_sdram_choose_req_want_activates[0:0] 1'0
sync always
update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0]
end
attribute \src "ls180.v:763.5-763.43"
- process $proc$ls180.v:763$3049
+ process $proc$ls180.v:763$3042
assign { } { }
assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0]
end
attribute \src "ls180.v:766.5-766.49"
- process $proc$ls180.v:766$3050
+ process $proc$ls180.v:766$3043
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0]
end
attribute \src "ls180.v:767.5-767.49"
- process $proc$ls180.v:767$3051
+ process $proc$ls180.v:767$3044
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0]
end
attribute \src "ls180.v:768.5-768.48"
- process $proc$ls180.v:768$3052
+ process $proc$ls180.v:768$3045
assign { } { }
assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0
sync always
update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0]
end
attribute \src "ls180.v:772.11-772.46"
- process $proc$ls180.v:772$3053
+ process $proc$ls180.v:772$3046
assign { } { }
assign $1\main_sdram_choose_req_valids[3:0] 4'0000
sync always
update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0]
end
attribute \src "ls180.v:774.11-774.45"
- process $proc$ls180.v:774$3054
+ process $proc$ls180.v:774$3047
assign { } { }
assign $1\main_sdram_choose_req_grant[1:0] 2'00
sync always
update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0]
end
attribute \src "ls180.v:776.12-776.36"
- process $proc$ls180.v:776$3055
+ process $proc$ls180.v:776$3048
assign { } { }
assign $0\main_sdram_nop_a[12:0] 13'0000000000000
sync always
sync init
end
attribute \src "ls180.v:777.11-777.35"
- process $proc$ls180.v:777$3056
+ process $proc$ls180.v:777$3049
assign { } { }
assign $0\main_sdram_nop_ba[1:0] 2'00
sync always
sync init
end
attribute \src "ls180.v:778.11-778.40"
- process $proc$ls180.v:778$3057
+ process $proc$ls180.v:778$3050
assign { } { }
assign $1\main_sdram_steerer_sel[1:0] 2'00
sync always
update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0]
end
attribute \src "ls180.v:779.5-779.31"
- process $proc$ls180.v:779$3058
+ process $proc$ls180.v:779$3051
assign { } { }
assign $0\main_sdram_steerer0[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:780.5-780.31"
- process $proc$ls180.v:780$3059
+ process $proc$ls180.v:780$3052
assign { } { }
assign $0\main_sdram_steerer1[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:782.32-782.63"
- process $proc$ls180.v:782$3060
+ process $proc$ls180.v:782$3053
assign { } { }
assign $0\main_sdram_trrdcon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:784.32-784.63"
- process $proc$ls180.v:784$3061
+ process $proc$ls180.v:784$3054
assign { } { }
assign $0\main_sdram_tfawcon_ready[0:0] 1'1
sync always
sync init
end
attribute \src "ls180.v:786.32-786.63"
- process $proc$ls180.v:786$3062
+ process $proc$ls180.v:786$3055
assign { } { }
assign $1\main_sdram_tccdcon_ready[0:0] 1'0
sync always
update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0]
end
attribute \src "ls180.v:787.5-787.36"
- process $proc$ls180.v:787$3063
+ process $proc$ls180.v:787$3056
assign { } { }
assign $1\main_sdram_tccdcon_count[0:0] 1'0
sync always
update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0]
end
attribute \src "ls180.v:789.32-789.63"
- process $proc$ls180.v:789$3064
+ process $proc$ls180.v:789$3057
assign { } { }
assign $1\main_sdram_twtrcon_ready[0:0] 1'0
sync always
update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0]
end
attribute \src "ls180.v:790.11-790.42"
- process $proc$ls180.v:790$3065
+ process $proc$ls180.v:790$3058
assign { } { }
assign $1\main_sdram_twtrcon_count[2:0] 3'000
sync always
update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0]
end
attribute \src "ls180.v:793.5-793.26"
- process $proc$ls180.v:793$3066
+ process $proc$ls180.v:793$3059
assign { } { }
assign $1\main_sdram_en0[0:0] 1'0
sync always
update \main_sdram_en0 $1\main_sdram_en0[0:0]
end
attribute \src "ls180.v:795.11-795.34"
- process $proc$ls180.v:795$3067
+ process $proc$ls180.v:795$3060
assign { } { }
assign $1\main_sdram_time0[4:0] 5'00000
sync always
update \main_sdram_time0 $1\main_sdram_time0[4:0]
end
attribute \src "ls180.v:796.5-796.26"
- process $proc$ls180.v:796$3068
+ process $proc$ls180.v:796$3061
assign { } { }
assign $1\main_sdram_en1[0:0] 1'0
sync always
update \main_sdram_en1 $1\main_sdram_en1[0:0]
end
attribute \src "ls180.v:798.11-798.34"
- process $proc$ls180.v:798$3069
+ process $proc$ls180.v:798$3062
assign { } { }
assign $1\main_sdram_time1[3:0] 4'0000
sync always
update \main_sdram_time1 $1\main_sdram_time1[3:0]
end
attribute \src "ls180.v:819.5-819.29"
- process $proc$ls180.v:819$3070
+ process $proc$ls180.v:819$3063
assign { } { }
assign $1\main_wb_sdram_ack[0:0] 1'0
sync always
update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0]
end
attribute \src "ls180.v:823.5-823.29"
- process $proc$ls180.v:823$3071
+ process $proc$ls180.v:823$3064
assign { } { }
assign $0\main_wb_sdram_err[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:824.12-824.40"
- process $proc$ls180.v:824$3072
+ process $proc$ls180.v:824$3065
assign { } { }
assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000
sync always
update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0]
end
attribute \src "ls180.v:825.12-825.42"
- process $proc$ls180.v:825$3073
+ process $proc$ls180.v:825$3066
assign { } { }
assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000
sync always
update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0]
end
attribute \src "ls180.v:827.11-827.38"
- process $proc$ls180.v:827$3074
+ process $proc$ls180.v:827$3067
assign { } { }
assign $1\main_litedram_wb_sel[1:0] 2'00
sync always
update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0]
end
attribute \src "ls180.v:828.5-828.32"
- process $proc$ls180.v:828$3075
+ process $proc$ls180.v:828$3068
assign { } { }
assign $1\main_litedram_wb_cyc[0:0] 1'0
sync always
update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0]
end
attribute \src "ls180.v:829.5-829.32"
- process $proc$ls180.v:829$3076
+ process $proc$ls180.v:829$3069
assign { } { }
assign $1\main_litedram_wb_stb[0:0] 1'0
sync always
update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0]
end
attribute \src "ls180.v:831.5-831.31"
- process $proc$ls180.v:831$3077
+ process $proc$ls180.v:831$3070
assign { } { }
assign $1\main_litedram_wb_we[0:0] 1'0
sync always
update \main_litedram_wb_we $1\main_litedram_wb_we[0:0]
end
attribute \src "ls180.v:832.5-832.31"
- process $proc$ls180.v:832$3078
+ process $proc$ls180.v:832$3071
assign { } { }
assign $1\main_converter_skip[0:0] 1'0
sync always
update \main_converter_skip $1\main_converter_skip[0:0]
end
attribute \src "ls180.v:833.5-833.34"
- process $proc$ls180.v:833$3079
+ process $proc$ls180.v:833$3072
assign { } { }
assign $1\main_converter_counter[0:0] 1'0
sync always
update \main_converter_counter $1\main_converter_counter[0:0]
end
attribute \src "ls180.v:835.12-835.40"
- process $proc$ls180.v:835$3080
+ process $proc$ls180.v:835$3073
assign { } { }
assign $1\main_converter_dat_r[31:0] 0
sync always
update \main_converter_dat_r $1\main_converter_dat_r[31:0]
end
attribute \src "ls180.v:836.5-836.29"
- process $proc$ls180.v:836$3081
+ process $proc$ls180.v:836$3074
assign { } { }
assign $1\main_cmd_consumed[0:0] 1'0
sync always
update \main_cmd_consumed $1\main_cmd_consumed[0:0]
end
attribute \src "ls180.v:837.5-837.31"
- process $proc$ls180.v:837$3082
+ process $proc$ls180.v:837$3075
assign { } { }
assign $1\main_wdata_consumed[0:0] 1'0
sync always
update \main_wdata_consumed $1\main_wdata_consumed[0:0]
end
attribute \src "ls180.v:841.12-841.47"
- process $proc$ls180.v:841$3083
+ process $proc$ls180.v:841$3076
assign { } { }
assign $1\main_uart_phy_storage[31:0] 9895604
sync always
update \main_uart_phy_storage $1\main_uart_phy_storage[31:0]
end
attribute \src "ls180.v:842.5-842.28"
- process $proc$ls180.v:842$3084
+ process $proc$ls180.v:842$3077
assign { } { }
assign $1\main_uart_phy_re[0:0] 1'0
sync always
update \main_uart_phy_re $1\main_uart_phy_re[0:0]
end
attribute \src "ls180.v:844.5-844.36"
- process $proc$ls180.v:844$3085
+ process $proc$ls180.v:844$3078
assign { } { }
assign $1\main_uart_phy_sink_ready[0:0] 1'0
sync always
update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0]
end
attribute \src "ls180.v:848.5-848.39"
- process $proc$ls180.v:848$3086
+ process $proc$ls180.v:848$3079
assign { } { }
assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0
sync always
update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0]
end
attribute \src "ls180.v:849.12-849.54"
- process $proc$ls180.v:849$3087
+ process $proc$ls180.v:849$3080
assign { } { }
assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0
sync always
update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0]
end
attribute \src "ls180.v:850.11-850.38"
- process $proc$ls180.v:850$3088
+ process $proc$ls180.v:850$3081
assign { } { }
assign $1\main_uart_phy_tx_reg[7:0] 8'00000000
sync always
update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0]
end
attribute \src "ls180.v:851.11-851.43"
- process $proc$ls180.v:851$3089
+ process $proc$ls180.v:851$3082
assign { } { }
assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000
sync always
update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0]
end
attribute \src "ls180.v:852.5-852.33"
- process $proc$ls180.v:852$3090
+ process $proc$ls180.v:852$3083
assign { } { }
assign $1\main_uart_phy_tx_busy[0:0] 1'0
sync always
update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0]
end
attribute \src "ls180.v:853.5-853.38"
- process $proc$ls180.v:853$3091
+ process $proc$ls180.v:853$3084
assign { } { }
assign $1\main_uart_phy_source_valid[0:0] 1'0
sync always
update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0]
end
attribute \src "ls180.v:855.5-855.38"
- process $proc$ls180.v:855$3092
+ process $proc$ls180.v:855$3085
assign { } { }
assign $0\main_uart_phy_source_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:856.5-856.37"
- process $proc$ls180.v:856$3093
+ process $proc$ls180.v:856$3086
assign { } { }
assign $0\main_uart_phy_source_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:857.11-857.51"
- process $proc$ls180.v:857$3094
+ process $proc$ls180.v:857$3087
assign { } { }
assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000
sync always
update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0]
end
attribute \src "ls180.v:858.5-858.39"
- process $proc$ls180.v:858$3095
+ process $proc$ls180.v:858$3088
assign { } { }
assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0
sync always
update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0]
end
attribute \src "ls180.v:859.12-859.54"
- process $proc$ls180.v:859$3096
+ process $proc$ls180.v:859$3089
assign { } { }
assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0
sync always
update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0]
end
attribute \src "ls180.v:861.5-861.30"
- process $proc$ls180.v:861$3097
+ process $proc$ls180.v:861$3090
assign { } { }
assign $1\main_uart_phy_rx_r[0:0] 1'0
sync always
update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0]
end
attribute \src "ls180.v:862.11-862.38"
- process $proc$ls180.v:862$3098
+ process $proc$ls180.v:862$3091
assign { } { }
assign $1\main_uart_phy_rx_reg[7:0] 8'00000000
sync always
update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0]
end
attribute \src "ls180.v:863.11-863.43"
- process $proc$ls180.v:863$3099
+ process $proc$ls180.v:863$3092
assign { } { }
assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000
sync always
update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0]
end
attribute \src "ls180.v:864.5-864.33"
- process $proc$ls180.v:864$3100
+ process $proc$ls180.v:864$3093
assign { } { }
assign $1\main_uart_phy_rx_busy[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:875.5-875.32"
- process $proc$ls180.v:875$3101
+ process $proc$ls180.v:875$3094
assign { } { }
assign $1\main_uart_tx_pending[0:0] 1'0
sync always
update \main_uart_tx_pending $1\main_uart_tx_pending[0:0]
end
attribute \src "ls180.v:877.5-877.30"
- process $proc$ls180.v:877$3102
+ process $proc$ls180.v:877$3095
assign { } { }
assign $1\main_uart_tx_clear[0:0] 1'0
sync always
update \main_uart_tx_clear $1\main_uart_tx_clear[0:0]
end
attribute \src "ls180.v:878.5-878.36"
- process $proc$ls180.v:878$3103
+ process $proc$ls180.v:878$3096
assign { } { }
assign $1\main_uart_tx_old_trigger[0:0] 1'0
sync always
update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0]
end
attribute \src "ls180.v:880.5-880.32"
- process $proc$ls180.v:880$3104
+ process $proc$ls180.v:880$3097
assign { } { }
assign $1\main_uart_rx_pending[0:0] 1'0
sync always
update \main_uart_rx_pending $1\main_uart_rx_pending[0:0]
end
attribute \src "ls180.v:882.5-882.30"
- process $proc$ls180.v:882$3105
+ process $proc$ls180.v:882$3098
assign { } { }
assign $1\main_uart_rx_clear[0:0] 1'0
sync always
update \main_uart_rx_clear $1\main_uart_rx_clear[0:0]
end
attribute \src "ls180.v:883.5-883.36"
- process $proc$ls180.v:883$3106
+ process $proc$ls180.v:883$3099
assign { } { }
assign $1\main_uart_rx_old_trigger[0:0] 1'0
sync always
update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0]
end
attribute \src "ls180.v:887.11-887.49"
- process $proc$ls180.v:887$3107
+ process $proc$ls180.v:887$3100
assign { } { }
assign $1\main_uart_eventmanager_status_w[1:0] 2'00
sync always
update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0]
end
attribute \src "ls180.v:891.11-891.50"
- process $proc$ls180.v:891$3108
+ process $proc$ls180.v:891$3101
assign { } { }
assign $1\main_uart_eventmanager_pending_w[1:0] 2'00
sync always
update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0]
end
attribute \src "ls180.v:892.11-892.48"
- process $proc$ls180.v:892$3109
+ process $proc$ls180.v:892$3102
assign { } { }
assign $1\main_uart_eventmanager_storage[1:0] 2'00
sync always
update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0]
end
attribute \src "ls180.v:893.5-893.37"
- process $proc$ls180.v:893$3110
+ process $proc$ls180.v:893$3103
assign { } { }
assign $1\main_uart_eventmanager_re[0:0] 1'0
sync always
update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0]
end
attribute \src "ls180.v:910.5-910.40"
- process $proc$ls180.v:910$3111
+ process $proc$ls180.v:910$3104
assign { } { }
assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:911.5-911.39"
- process $proc$ls180.v:911$3112
+ process $proc$ls180.v:911$3105
assign { } { }
assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:919.5-919.38"
- process $proc$ls180.v:919$3113
+ process $proc$ls180.v:919$3106
assign { } { }
assign $1\main_uart_tx_fifo_readable[0:0] 1'0
sync always
update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0]
end
attribute \src "ls180.v:926.11-926.42"
- process $proc$ls180.v:926$3114
+ process $proc$ls180.v:926$3107
assign { } { }
assign $1\main_uart_tx_fifo_level0[4:0] 5'00000
sync always
update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0]
end
attribute \src "ls180.v:927.5-927.37"
- process $proc$ls180.v:927$3115
+ process $proc$ls180.v:927$3108
assign { } { }
assign $0\main_uart_tx_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:928.11-928.43"
- process $proc$ls180.v:928$3116
+ process $proc$ls180.v:928$3109
assign { } { }
assign $1\main_uart_tx_fifo_produce[3:0] 4'0000
sync always
update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0]
end
attribute \src "ls180.v:929.11-929.43"
- process $proc$ls180.v:929$3117
+ process $proc$ls180.v:929$3110
assign { } { }
assign $1\main_uart_tx_fifo_consume[3:0] 4'0000
sync always
update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0]
end
attribute \src "ls180.v:930.11-930.46"
- process $proc$ls180.v:930$3118
+ process $proc$ls180.v:930$3111
assign { } { }
assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000
sync always
update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0]
end
attribute \src "ls180.v:956.5-956.38"
- process $proc$ls180.v:956$3119
+ process $proc$ls180.v:956$3112
assign { } { }
assign $1\main_uart_rx_fifo_readable[0:0] 1'0
sync always
update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0]
end
attribute \src "ls180.v:963.11-963.42"
- process $proc$ls180.v:963$3120
+ process $proc$ls180.v:963$3113
assign { } { }
assign $1\main_uart_rx_fifo_level0[4:0] 5'00000
sync always
update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0]
end
attribute \src "ls180.v:964.5-964.37"
- process $proc$ls180.v:964$3121
+ process $proc$ls180.v:964$3114
assign { } { }
assign $0\main_uart_rx_fifo_replace[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:965.11-965.43"
- process $proc$ls180.v:965$3122
+ process $proc$ls180.v:965$3115
assign { } { }
assign $1\main_uart_rx_fifo_produce[3:0] 4'0000
sync always
update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0]
end
attribute \src "ls180.v:966.11-966.43"
- process $proc$ls180.v:966$3123
+ process $proc$ls180.v:966$3116
assign { } { }
assign $1\main_uart_rx_fifo_consume[3:0] 4'0000
sync always
update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0]
end
attribute \src "ls180.v:967.11-967.46"
- process $proc$ls180.v:967$3124
+ process $proc$ls180.v:967$3117
assign { } { }
assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000
sync always
update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0]
end
attribute \src "ls180.v:982.5-982.27"
- process $proc$ls180.v:982$3125
+ process $proc$ls180.v:982$3118
assign { } { }
assign $0\main_uart_reset[0:0] 1'0
sync always
sync init
end
attribute \src "ls180.v:983.12-983.40"
- process $proc$ls180.v:983$3126
+ process $proc$ls180.v:983$3119
assign { } { }
assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000
sync always
update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0]
end
attribute \src "ls180.v:984.5-984.27"
- process $proc$ls180.v:984$3127
+ process $proc$ls180.v:984$3120
assign { } { }
assign $1\main_gpio_oe_re[0:0] 1'0
sync always
update \main_gpio_oe_re $1\main_gpio_oe_re[0:0]
end
attribute \src "ls180.v:985.12-985.36"
- process $proc$ls180.v:985$3128
+ process $proc$ls180.v:985$3121
assign { } { }
assign $1\main_gpio_status[15:0] 16'0000000000000000
sync always
update \main_gpio_status $1\main_gpio_status[15:0]
end
attribute \src "ls180.v:987.12-987.41"
- process $proc$ls180.v:987$3129
+ process $proc$ls180.v:987$3122
assign { } { }
assign $1\main_gpio_out_storage[15:0] 16'0000000000000000
sync always
update \main_gpio_out_storage $1\main_gpio_out_storage[15:0]
end
attribute \src "ls180.v:988.5-988.28"
- process $proc$ls180.v:988$3130
+ process $proc$ls180.v:988$3123
assign { } { }
assign $1\main_gpio_out_re[0:0] 1'0
sync always
update \main_gpio_out_re $1\main_gpio_out_re[0:0]
end
attribute \src "ls180.v:994.5-994.32"
- process $proc$ls180.v:994$3131
+ process $proc$ls180.v:994$3124
assign { } { }
assign $1\main_spimaster2_done[0:0] 1'0
sync always
update \main_spimaster2_done $1\main_spimaster2_done[0:0]
end
attribute \src "ls180.v:995.5-995.31"
- process $proc$ls180.v:995$3132
+ process $proc$ls180.v:995$3125
assign { } { }
assign $1\main_spimaster3_irq[0:0] 1'0
sync always
update \main_spimaster3_irq $1\main_spimaster3_irq[0:0]
end
attribute \src "ls180.v:997.11-997.38"
- process $proc$ls180.v:997$3133
+ process $proc$ls180.v:997$3126
assign { } { }
assign $1\main_spimaster5_miso[7:0] 8'00000000
sync always
projects / soclayout.git / commitdiff