output countzero ilang

diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py
index c6b781adba06745ea1c195d3026ec94b287860eb..60185196153680196f5c590704f9e3ca826f1004 100644 (file)
--- a/src/soc/countzero/test/test_countzero.py
+++ b/src/soc/countzero/test/test_countzero.py
@@ -1,5 +1,6 @@
 # https://github.com/antonblanchard/microwatt/blob/master/countzero_tb.vhdl
 from nmigen import Module, Signal
+from nmigen.cli import rtlil
 from nmigen.back.pysim import Simulator, Delay
 from nmigen.test.utils import FHDLTestCase
 import unittest
@@ -95,5 +96,10 @@ class ZeroCounterTestCase(FHDLTestCase):
 
 
 if __name__ == "__main__":
-    unittest.main()
 
+    dut = ZeroCounter()
+    vl = rtlil.convert(dut, ports=dut.ports())
+    with open("countzero.il", "w") as f:
+        f.write(vl)
+
+    unittest.main()