TODO comments about using MSRspec

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 72e0834fc9553c0d87b18ff06cbf3690604e5fb8..cb17807d89031d1592c96a42c17da8523b4e8856 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -222,7 +222,12 @@ class PortInterfaceBase(Elaboratable):
         pi = self.pi
         comb += lds.eq(pi.is_ld_i)  # ld-req signals
         comb += sts.eq(pi.is_st_i)  # st-req signals
+
+        # TODO: construct an MSRspec here and pass it over in
+        # self.set_rd_addr and set_wr_addr below rather than just pr
         pr = ~pi.priv_mode
+        dr = ~pi.virt_mode   # not yet used
+        sf = self.mode_32bit   # not yet used
 
         # detect busy "edge"
         busy_delay = Signal()