add axi4 reg #defines

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 7fbf58bdc9236f53d8d836d74e1d0a9717023c1a..c5824b2dd39e3dd3ee812e34fb75c895ba311a07 100644 (file)
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -8,6 +8,8 @@ package slow_peripherals;
        import Semi_FIFOF::*;
        import AXI4Lite_AXI4_Bridge::*;
        `include "instance_defines.bsv"
+    /* ==== define the AXI Addresses ==== */
+{2}
        /*===========================*/
        /*=== package imports ===*/
        import Clocks::*;

diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py
index 7df7a43bf3a7dc80f3acde913efd22ad3654f562..25e5c0aacb58a27a1590b9d7e7c5ec9fd4b57a88 100644 (file)
--- a/src/bsv/interface_decl.py
+++ b/src/bsv/interface_decl.py
@@ -164,7 +164,7 @@ class Interface(object):
     def getifacetype(self, name):
         for p in self.pinspecs:
             fname = "%s_%s" % (self.ifacename, p['name'])
-            #print "search", self.ifacename, name, fname
+            # print "search", self.ifacename, name, fname
             if fname == name:
                 if p.get('action'):
                     return 'out'
@@ -192,7 +192,7 @@ class Interface(object):
         """
         if not self.ganged:
             return ''  # when self.ganged is None
-        #print self.ganged
+        # print self.ganged
         res = []
         for (k, pnames) in self.ganged.items():
             name = self.pname('%senable' % k).format(*args)
@@ -246,7 +246,7 @@ class Interface(object):
     def ifacefmtpin(self, pin):
         decfn = self.ifacefmtdecfn2
         outfn = self.ifacefmtoutfn
-        #print pin, pin.outenmode
+        # print pin, pin.outenmode
         if pin.outenmode:
             decfn = self.ifacefmtdecfn3
             outfn = self.ifacefmtoutenfn
@@ -268,6 +268,11 @@ class Interface(object):
             return ''
         return self.slow.ifacedecl().format(count, self.ifacename)
 
+    def axi_reg_def(self, start, count):
+        if not self.slow:
+            return ('', 0)
+        return self.slow.axi_reg_def(start, self.ifacename, count)
+
 
 class MuxInterface(Interface):
 
@@ -342,14 +347,26 @@ class Interfaces(InterfacesBase):
                 ret.append(self.data[name].slowifdecl(i))
         return '\n'.join(list(filter(None, ret)))
 
+    def axi_reg_def(self, *args):
+        ret = []
+        start = 0x00011100  # start of AXI peripherals address
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                x = self.data[name].axi_reg_def(start, i)
+                print ("ifc", name, x)
+                (rdef, offs) = x
+                ret.append(rdef)
+                start += offs
+        return '\n'.join(list(filter(None, ret)))
+
 
 # ========= Interface declarations ================ #
 
-mux_interface = MuxInterface('cell',
+mux_interface=MuxInterface('cell',
                              [{'name': 'mux', 'ready': False, 'enabled': False,
                                'bitspec': '{1}', 'action': True}])
 
-io_interface = IOInterface(
+io_interface=IOInterface(
     'io',
     [{'name': 'cell_out', 'enabled': True, },
      {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
@@ -365,12 +382,12 @@ io_interface = IOInterface(
 # basic test
 if __name__ == '__main__':
 
-    uartinterface_decl = Interface('uart',
+    uartinterface_decl=Interface('uart',
                                    [{'name': 'rx'},
                                     {'name': 'tx', 'action': True},
                                     ])
 
-    twiinterface_decl = Interface('twi',
+    twiinterface_decl=Interface('twi',
                                   [{'name': 'sda', 'outen': True},
                                    {'name': 'scl', 'outen': True},
                                    ])

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 90f7b43237bbefc4bca4497ac27a321975494773..9fa225148c404701bcdf6d3e00cef9477ee23dc8 100644 (file)
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -1,12 +1,23 @@
 class PBase(object):
     pass
 
-    def axi_reg_def(self, start, name, ifacenum):
+    def axibase(self, name, ifacenum):
+        name = name.upper()
+        return "%(name)s%(ifacenum)dBase" % locals()
+
+    def axiend(self, name, ifacenum):
         name = name.upper()
-        offs = self.num_axi_regs32()*4
-        end = start + offs - 1
-        return ("    `define%(name)s%(ifacenum)dBase 'h%(start)08x'\n" \
-                "    `define%(name)s%(ifacenum)dEnd  'h%(end)08x'\n" % locals(),
+        return "%(name)s%(ifacenum)dEnd" % locals()
+
+    def axi_reg_def(self, start, name, ifacenum):
+        name=name.upper()
+        offs=self.num_axi_regs32() * 4 * 16
+        end=start + offs - 1
+        bname=self.axibase(name, ifacenum)
+        bend=self.axiend(name, ifacenum)
+        comment = "%d 32-bit regs" % self.num_axi_regs32()
+        return ("    `define%(bname)s 'h%(start)08X\n"
+                "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
                 offs)
 
 
@@ -15,7 +26,7 @@ class uart(PBase):
         return "          import Uart16550         :: *;"
 
     def ifacedecl(self):
-        return "            interface RS232_PHY_Ifc uart{0}_coe;\n" \
+        return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
                "            method Bit#(1) uart{0}_intr;"
 
     def num_axi_regs32(self):
@@ -24,7 +35,7 @@ class uart(PBase):
 
 class rs232(PBase):
     def importfn(self):
-        return "        import Uart_bs::*;\n" \
+        return "        import Uart_bs::*;\n" + \
                "        import RS232_modified::*;"
 
     def ifacedecl(self):
@@ -39,7 +50,7 @@ class twi(PBase):
         return "        import I2C_top           :: *;"
 
     def ifacedecl(self):
-        return "            interface I2C_out i2c{0}_out;\n" \
+        return "            interface I2C_out i2c{0}_out;\n" + \
                "            method Bit#(1) i2c{0}_isint;"
 
     def num_axi_regs32(self):
@@ -51,7 +62,7 @@ class qspi(PBase):
         return "        import qspi              :: *;"
 
     def ifacedecl(self):
-        return "            interface QSPI_out qspi{0}_out;\n" \
+        return "            interface QSPI_out qspi{0}_out;\n" + \
                "            method Bit#(1) qspi{0}_isint;"
 
     def num_axi_regs32(self):
@@ -71,8 +82,8 @@ class pwm(PBase):
 
 class gpio(PBase):
     def importfn(self):
-        return "     import pinmux::*;\n" \
-               "     import mux::*;\n" \
+        return "     import pinmux::*;\n" + \
+               "     import mux::*;\n" + \
                "     import gpio::*;\n"
 
     def ifacedecl(self):

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 7d33d6f387d29e888cdf87d24f0663d7e67c5661..560704e1890f55c3f7b6fd00fa5de27bf2fb66e4 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -101,8 +101,9 @@ def write_slow(slow, template, p, ifaces):
         template = bsv_file.read()
     imports = ifaces.slowimport()
     ifdecl = ifaces.slowifdecl()
+    regdef = ifaces.axi_reg_def()
     with open(slow, "w") as bsv_file:
-        bsv_file.write(template.format(imports, ifdecl))
+        bsv_file.write(template.format(imports, ifdecl, regdef))
 
 
 def write_bus(bus, p, ifaces):
@@ -354,10 +355,10 @@ def write_bvp(bvp, p, ifaces):
             decl.append(muxdec .format(npins, bank))
             idec.append(gpioifc.format(bank))
             idec.append(muxifc.format(bank))
-        print (dir(ifaces))
-        print (ifaces.items())
-        print (dir(ifaces['gpioa']))
-        print (ifaces['gpioa'].pinspecs)
+        print dir(ifaces)
+        print ifaces.items()
+        print dir(ifaces['gpioa'])
+        print ifaces['gpioa'].pinspecs
         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
         gpiocfg = '\n'.join(cfg)
         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))