from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
+from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
-from soc.fu.div.pipeline import DivBasePipe
-from soc.fu.div.pipe_data import DivPipeSpec
-import random
-
-class TestCase:
- def __init__(self, program, regs, sprs, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
+from soc.fu.test.common import (TestCase, DIVHelpers)
+from soc.fu.div.pipeline import DIVBasePipe
+from soc.fu.div.pipe_data import DIVPipeSpec
+import random
-def set_alu_inputs(alu, dec2, sim):
- # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
- # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
- # and place it into data_i.b
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to DIVFunctionUnit input regspec
+ """
+ res = {}
- reg3_ok = yield dec2.e.read_reg3.ok
+ # RA (or RC)
reg1_ok = yield dec2.e.read_reg1.ok
- assert reg3_ok != reg1_ok
- if reg3_ok:
- data1 = yield dec2.e.read_reg3.data
- data1 = sim.gpr(data1).value
- elif reg1_ok:
+ if reg1_ok:
data1 = yield dec2.e.read_reg1.data
- data1 = sim.gpr(data1).value
- else:
- data1 = 0
+ res['ra'] = sim.gpr(data1).value
- yield alu.p.data_i.a.eq(data1)
-
- # If there's an immediate, set the B operand to that
+ # RB (or immediate)
reg2_ok = yield dec2.e.read_reg2.ok
- imm_ok = yield dec2.e.imm_data.imm_ok
- if imm_ok:
- data2 = yield dec2.e.imm_data.imm
- elif reg2_ok:
+ if reg2_ok:
data2 = yield dec2.e.read_reg2.data
- data2 = sim.gpr(data2).value
- else:
- data2 = 0
- yield alu.p.data_i.b.eq(data2)
+ res['rb'] = sim.gpr(data2).value
+
+ # XER.ca
+ cry_in = yield dec2.e.input_carry
+ if cry_in == CryIn.CA.value:
+ carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+ carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+ res['xer_ca'] = carry | (carry32<<1)
+
+ # XER.so
+ oe = yield dec2.e.oe.data[0] & dec2.e.oe.ok
+ if oe:
+ so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ res['xer_so'] = so
+
+ print ("alu get_cu_inputs", res)
+
+ return res
+
+
+def set_alu_inputs(alu, dec2, sim):
+ # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
+ # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
+ # and place it into data_i.b
-def set_extra_alu_inputs(alu, dec2, sim):
- carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
- yield alu.p.data_i.xer_ca[0].eq(carry)
- yield alu.p.data_i.xer_ca[1].eq(carry32)
- so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
- yield alu.p.data_i.xer_so.eq(so)
+ inp = yield from get_cu_inputs(dec2, sim)
+ yield from DIVHelpers.set_int_ra(alu, dec2, inp)
+ yield from DIVHelpers.set_int_rb(alu, dec2, inp)
+
+ yield from DIVHelpers.set_xer_ca(alu, dec2, inp)
+ yield from DIVHelpers.set_xer_so(alu, dec2, inp)
# This test bench is a bit different than is usual. Initially when I
# should have. However, this was really slow, since it needed to
# create and tear down the dut and simulator for every test case.
-# Now, instead of doing that, every test case in ALUTestCase puts some
+# Now, instead of doing that, every test case in DIVTestCase puts some
# data into the test_data list below, describing the instructions to
# be tested and the initial state. Once all the tests have been run,
# test_data gets passed to TestRunner which then sets up the DUT and
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
+class DIVTestCase(FHDLTestCase):
+ test_data = []
-class DivTestCase(FHDLTestCase):
def __init__(self, name):
super().__init__(name)
self.test_name = name
- def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
- tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
- test_data.append(tc)
+ def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
+ tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
+ self.test_data.append(tc)
+
+ def test_1_regression(self):
+ lst = [f"extsw 3, 1"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xb6a1fc6c8576af91
+ self.run_tst_program(Program(lst), initial_regs)
+ lst = [f"subf 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x3d7f3f7ca24bac7b
+ initial_regs[2] = 0xf6b2ac5e13ee15c2
+ self.run_tst_program(Program(lst), initial_regs)
+ lst = [f"subf 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x833652d96c7c0058
+ initial_regs[2] = 0x1c27ecff8a086c1a
+ self.run_tst_program(Program(lst), initial_regs)
+ lst = [f"extsb 3, 1"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x7f9497aaff900ea0
+ self.run_tst_program(Program(lst), initial_regs)
+ lst = [f"add. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xc523e996a8ff6215
+ initial_regs[2] = 0xe1e5b9cc9864c4a8
+ self.run_tst_program(Program(lst), initial_regs)
+ lst = [f"add 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x2e08ae202742baf8
+ initial_regs[2] = 0x86c43ece9efe5baa
+ self.run_tst_program(Program(lst), initial_regs)
def test_rand(self):
- insns = ["and", "or", "xor"]
+ insns = ["add", "add.", "subf"]
for i in range(40):
choice = random.choice(insns)
lst = [f"{choice} 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- initial_regs[2] = random.randint(0, (1 << 64)-1)
+ initial_regs[1] = random.randint(0, (1<<64)-1)
+ initial_regs[2] = random.randint(0, (1<<64)-1)
self.run_tst_program(Program(lst), initial_regs)
- def test_rand_imm_logical(self):
- insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
+ def test_rand_imm(self):
+ insns = ["addi", "addis", "subfic"]
for i in range(10):
choice = random.choice(insns)
- imm = random.randint(0, (1 << 16)-1)
+ imm = random.randint(-(1<<15), (1<<15)-1)
lst = [f"{choice} 3, 1, {imm}"]
print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
-
- def test_cntz(self):
- insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
- for i in range(100):
- choice = random.choice(insns)
- lst = [f"{choice} 3, 1"]
- print(lst)
- initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[1] = random.randint(0, (1<<64)-1)
self.run_tst_program(Program(lst), initial_regs)
- def test_parity(self):
- insns = ["prtyw", "prtyd"]
+ def test_0_adde(self):
+ lst = ["adde. 5, 6, 7"]
for i in range(10):
- choice = random.choice(insns)
- lst = [f"{choice} 3, 1"]
- print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[6] = random.randint(0, (1<<64)-1)
+ initial_regs[7] = random.randint(0, (1<<64)-1)
+ initial_sprs = {}
+ xer = SelectableInt(0, 64)
+ xer[XER_bits['CA']] = 1
+ initial_sprs[special_sprs['XER']] = xer
+ self.run_tst_program(Program(lst), initial_regs, initial_sprs)
+
+ def test_cmp(self):
+ lst = ["subf. 1, 6, 7",
+ "cmp cr2, 1, 6, 7"]
+ initial_regs = [0] * 32
+ initial_regs[6] = 0x10
+ initial_regs[7] = 0x05
+ self.run_tst_program(Program(lst), initial_regs, {})
- def test_popcnt(self):
- insns = ["popcntb", "popcntw", "popcntd"]
+ def test_extsb(self):
+ insns = ["extsb", "extsh", "extsw"]
for i in range(10):
choice = random.choice(insns)
lst = [f"{choice} 3, 1"]
print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[1] = random.randint(0, (1<<64)-1)
self.run_tst_program(Program(lst), initial_regs)
- def test_popcnt_edge(self):
- insns = ["popcntb", "popcntw", "popcntd"]
- for choice in insns:
- lst = [f"{choice} 3, 1"]
- initial_regs = [0] * 32
- initial_regs[1] = -1
- self.run_tst_program(Program(lst), initial_regs)
-
- def test_cmpb(self):
- lst = ["cmpb 3, 1, 2"]
- initial_regs = [0] * 32
- initial_regs[1] = 0xdeadbeefcafec0de
- initial_regs[2] = 0xd0adb0000afec1de
- self.run_tst_program(Program(lst), initial_regs)
-
- def test_bpermd(self):
- lst = ["bpermd 3, 1, 2"]
+ def test_cmpeqb(self):
+ lst = ["cmpeqb cr1, 1, 2"]
for i in range(20):
initial_regs = [0] * 32
- initial_regs[1] = 1<<random.randint(0,63)
- initial_regs[2] = 0xdeadbeefcafec0de
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = i
+ initial_regs[2] = 0x0001030507090b0f
+ self.run_tst_program(Program(lst), initial_regs, {})
def test_ilang(self):
- pspec = DivPipeSpec(id_wid=2)
- alu = DivBasePipe(pspec)
+ pspec = DIVPipeSpec(id_wid=2)
+ alu = DIVBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
- with open("logical_pipeline.il", "w") as f:
+ with open("alu_pipeline.il", "w") as f:
f.write(vl)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = DivPipeSpec(id_wid=2)
- m.submodules.alu = alu = DivBasePipe(pspec)
+ pspec = DIVPipeSpec(id_wid=2)
+ m.submodules.alu = alu = DIVBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
comb += alu.p.valid_i.eq(1)
sim = Simulator(m)
sim.add_clock(1e-6)
-
def process():
for test in self.test_data:
print(test.name)
program = test.program
self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, 0)
+ sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
- index = simulator.pc.CIA.value//4
+ index = sim.pc.CIA.value//4
while index < len(instructions):
ins, code = instructions[index]
- print("0x{:X}".format(ins & 0xffffffff))
+ print("instruction: 0x{:X}".format(ins & 0xffffffff))
print(code)
+ if 'XER' in sim.spr:
+ so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+ ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+ print ("before: so/ov/32", so, ov, ov32)
# ask the decoder to decode this binary data (endian'd)
yield pdecode2.dec.bigendian.eq(0) # little / big?
yield instruction.eq(ins) # raw binary instr.
yield Settle()
fn_unit = yield pdecode2.e.fn_unit
- self.assertEqual(fn_unit, Function.LOGICAL.value, code)
- yield from set_alu_inputs(alu, pdecode2, simulator)
- yield from set_extra_alu_inputs(alu, pdecode2, simulator)
+ self.assertEqual(fn_unit, Function.DIV.value)
+ yield from set_alu_inputs(alu, pdecode2, sim)
yield
opname = code.split(' ')[0]
- yield from simulator.call(opname)
- index = simulator.pc.CIA.value//4
+ yield from sim.call(opname)
+ index = sim.pc.CIA.value//4
vld = yield alu.n.valid_o
while not vld:
yield
vld = yield alu.n.valid_o
yield
- alu_out = yield alu.n.data_o.o
+ alu_out = yield alu.n.data_o.o.data
out_reg_valid = yield pdecode2.e.write_reg.ok
if out_reg_valid:
write_reg_idx = yield pdecode2.e.write_reg.data
- expected = simulator.gpr(write_reg_idx).value
+ expected = sim.gpr(write_reg_idx).value
print(f"expected {expected:x}, actual: {alu_out:x}")
self.assertEqual(expected, alu_out, code)
yield from self.check_extra_alu_outputs(alu, pdecode2,
- simulator, code)
+ sim, code)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
+ traces=[]):
sim.run()
def check_extra_alu_outputs(self, alu, dec2, sim, code):
rc = yield dec2.e.rc.data
+ op = yield dec2.e.insn_type
+ cridx_ok = yield dec2.e.write_cr.ok
+ cridx = yield dec2.e.write_cr.data
+
+ print ("check extra output", repr(code), cridx_ok, cridx)
if rc:
- cr_expected = sim.crl[0].get_range().value
+ self.assertEqual(cridx, 0, code)
+
+ if cridx_ok:
+ cr_expected = sim.crl[cridx].get_range().value
cr_actual = yield alu.n.data_o.cr0.data
- self.assertEqual(cr_expected, cr_actual, code)
+ print ("CR", cridx, cr_expected, cr_actual)
+ self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
+
+ cry_out = yield dec2.e.output_carry
+ if cry_out:
+ expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+ real_carry = yield alu.n.data_o.xer_ca.data[0] # XXX CA not CA32
+ self.assertEqual(expected_carry, real_carry, code)
+ expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+ real_carry32 = yield alu.n.data_o.xer_ca.data[1] # XXX CA32
+ self.assertEqual(expected_carry32, real_carry32, code)
+
+ oe = yield dec2.e.oe.oe
+ oe_ok = yield dec2.e.oe.ok
+ if oe and oe_ok:
+ expected_so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ real_so = yield alu.n.data_o.xer_so.data[0]
+ self.assertEqual(expected_so, real_so, code)
+ expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+ real_ov = yield alu.n.data_o.xer_ov.data[0] # OV bit
+ self.assertEqual(expected_ov, real_ov, code)
+ expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+ real_ov32 = yield alu.n.data_o.xer_ov.data[1] # OV32 bit
+ self.assertEqual(expected_ov32, real_ov32, code)
+ print ("after: so/ov/32", real_so, real_ov, real_ov32)
+ else:
+ # if OE not enabled, XER SO and OV must correspondingly be false
+ so_ok = yield alu.n.data_o.xer_so.ok
+ ov_ok = yield alu.n.data_o.xer_ov.ok
+ self.assertEqual(so_ok, False, code)
+ self.assertEqual(ov_ok, False, code)
+
if __name__ == "__main__":
unittest.main(exit=False)
suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ suite.addTest(TestRunner(DIVTestCase.test_data))
runner = unittest.TextTestRunner()
runner.run(suite)
projects / soc.git / commitdiff