yield blank so test passes

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 7c9b8b07d0ae9ca325af4ac20425653f019bf87f..d95389cf9bf62ff60c616f3fac3dc72644be46ed 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -414,11 +414,11 @@ class CompUnitParallelTest:
 
     def rd(self, rd_idx):
         # monitor self.dut.rd.req[rd_idx] and sets dut.rd.go[idx] for one cycle
-        pass
+        yield
 
     def wr(self, wr_idx):
         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
-        pass
+        yield
 
 def test_compunit_regspec1():
     from alu_hier import ALU