Add missing ports to the test ALU

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 99ff39e47f287ff4125ea025c249ddfe4804c207..5b1968c2a19a085a478b179380fad3f205f60cce 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -278,6 +278,10 @@ class ALU(Elaboratable):
         yield self.a
         yield self.b
         yield self.o
+        yield self.p.valid_i
+        yield self.p.ready_o
+        yield self.n.valid_o
+        yield self.n.ready_i
 
     def ports(self):
         return list(self)