correction on single bit flags

diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py
index 213ab3e2fb7761f400ee2e830b159a6f9585c9db..1f77842e1907fa9ca7ef7214207fbbdcdc839529 100644 (file)
--- a/src/decoder/power_decoder.py
+++ b/src/decoder/power_decoder.py
@@ -40,7 +40,7 @@ class PowerOp:
                ]
         for bit in single_bit_flags:
             sig = getattr(self, get_signal_name(bit))
-            res.append(sig.eq(0))
+            res.append(sig.eq(int(row.get(bit, 0))))
         return res
 
     def ports(self):