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raw | patch | inline | side by side (parent: caceb71)
cut/paste error writing to wrong vcd file
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 10 Jul 2020 08:44:27 +0000 (09:44 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 10 Jul 2020 08:44:39 +0000 (09:44 +0100)
src/soc/fu/mul/test/test_pipe_caller.py patch | blob | history

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index cda81076a91a71cb3156aefab72a75acbdb24e52..44f5a09e73ff62a6c92b5bc98490c3d836279374 100644 (file)
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -215,7 +215,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
         sim.add_sync_process(process)
-        with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
+        with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
                             traces=[]):
             sim.run()