add modsw regression

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index bd22c81de38d03ba88e85daed504bc608188d5c0..c2b8b119ef67f35109924ed5474e7e56e633fe15 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -11,6 +11,14 @@ from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
 
 
 class DivTestCases(TestAccumulatorBase):
+    def case_modsw_regression(self):
+        lst = ["modsw 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        initial_regs[2] = 0x2
+        with Program(lst, bigendian) as prog:
+            self.add_case(prog, initial_regs)
+
     def case_divweu_regression(self):
         # simulator is wrong, FSM and power-instruction-analyzer both correct
         lst = ["divweu 3, 1, 2"]