move FPAddStage0Data to separate module

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index fd90887932704ac0623a77411bb320bb29a439de..e5845b4476a7ffb7842239f04b0d05ec582dcfd7 100644 (file)
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -9,25 +9,9 @@ from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
 
-from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class FPAddStage0Data:
-
-    def __init__(self, pspec):
-        width = pspec.width
-        self.z = FPNumBaseRecord(width, False)
-        self.out_do_z = Signal(reset_less=True)
-        self.oz = Signal(width, reset_less=True)
-        self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def eq(self, i):
-        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
+from ieee754.fpadd.datastruct import FPAddStage0Data
 
 
 class FPAddStage0Mod(PipeModBase):
@@ -51,10 +35,10 @@ class FPAddStage0Mod(PipeModBase):
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
         comb += [seq.eq(self.i.a.s == self.i.b.s),
-                     mge.eq(self.i.a.m >= self.i.b.m),
-                     am0.eq(Cat(self.i.a.m, 0)),
-                     bm0.eq(Cat(self.i.b.m, 0))
-                    ]
+                 mge.eq(self.i.a.m >= self.i.b.m),
+                 am0.eq(Cat(self.i.a.m, 0)),
+                 bm0.eq(Cat(self.i.b.m, 0))
+                ]
 
         # same-sign (both negative or both positive) add mantissas
         with m.If(~self.i.out_do_z):

diff --git a/src/ieee754/fpadd/datastruct.py b/src/ieee754/fpadd/datastruct.py
new file mode 100644 (file)
index 0000000..e2ca942
--- /dev/null
+++ b/src/ieee754/fpadd/datastruct.py
@@ -0,0 +1,26 @@
+"""IEEE754 Floating Point Adder Pipeline
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+"""
+
+from nmigen import Module, Signal
+
+from ieee754.fpcommon.fpbase import FPNumBaseRecord
+from ieee754.fpcommon.getop import FPPipeContext
+
+
+class FPAddStage0Data:
+
+    def __init__(self, pspec):
+        width = pspec.width
+        self.z = FPNumBaseRecord(width, False)
+        self.out_do_z = Signal(reset_less=True)
+        self.oz = Signal(width, reset_less=True)
+        self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits
+        self.ctx = FPPipeContext(pspec)
+        self.muxid = self.ctx.muxid
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+                self.tot.eq(i.tot), self.ctx.eq(i.ctx)]