Minor changes to test for caller.py, still not working at all

diff --git a/libreriscv b/libreriscv
index d38dcfdcc6923a03b8b3ac0ff8d03781dc6e7e80..6c7c31673fad55da82c22fbbcac3f9b5c49e6cc7 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit d38dcfdcc6923a03b8b3ac0ff8d03781dc6e7e80
+Subproject commit 6c7c31673fad55da82c22fbbcac3f9b5c49e6cc7

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 7bd2ca2180b901f88f684e37f51d2841b4f0ee10..f177042def5ce66dd94db196c8c27772669caddb 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -55,7 +55,7 @@ class GPR(dict):
 
 
 class ISACaller:
-    # decoder2 - an instance of power_decoder2 
+    # decoder2 - an instance of power_decoder2
     # regfile - a list of initial values for the registers
     def __init__(self, decoder2, regfile):
         self.gpr = GPR(decoder2, regfile)
@@ -63,11 +63,16 @@ class ISACaller:
         self.namespace = {'GPR': self.gpr,
                           'MEM': self.mem,
                           'memassign': self.memassign
-                         }
+                          }
 
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)
 
+    def call(self, name):
+        function, read_regs, uninit_regs, write_regs = self.instrs[name]
+
+
+
 
 def inject(context):
     """ Decorator factory. """

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 783f68861e53e9888f1982fdad95699262079a74..9d693a42c507b3efa00aa2061bd829376ec1106f 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -42,7 +42,7 @@ class DecoderTestCase(FHDLTestCase):
         instruction = Signal(32)
 
         pdecode = create_pdecode()
-        simulator = ISACaller(pdecode, [0] * 32)
+        simulator = fixedarith(pdecode, [0] * 32)
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
@@ -50,15 +50,17 @@ class DecoderTestCase(FHDLTestCase):
         gen = generator.generate_instructions()
 
         def process():
-            for ins in gen:
+            for ins, code in zip(gen, generator.assembly.splitlines()):
 
                 print("0x{:X}".format(ins & 0xffffffff))
+                print(code)
 
                 # ask the decoder to decode this binary data (endian'd)
                 yield pdecode2.dec.bigendian.eq(0)  # little / big?
                 yield instruction.eq(ins)          # raw binary instr.
                 yield Delay(1e-6)
-                yield from simulator.execute_op(pdecode2)
+                opname = code.split(' ')[0]
+                yield from simulator.call(opname)
 
         sim.add_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
@@ -67,7 +69,7 @@ class DecoderTestCase(FHDLTestCase):
         return simulator
 
     def test_addi(self):
-        lst = ["addi 1, 0, 0x1234",]
+        lst = ["addi 1, 0, 0x1234"]
         with Program(lst) as program:
             self.run_test_program(program)