rename JTAG port in adder test experiments10_verilog (success compile)

diff --git a/experiments10/coriolis2/ioring.py b/experiments10/coriolis2/ioring.py
index 3842e0ed8c0e480a2e9e91ccfe773e9ef52adbef..33522ca5c18b06c04ae3989d88ff8cc96fb10bf1 100644 (file)
--- a/experiments10/coriolis2/ioring.py
+++ b/experiments10/coriolis2/ioring.py
@@ -23,10 +23,10 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
         [ 'p_f2'    , 'f(2)',   'f(2)' ], # , 'f_oe' ],
         [ 'p_f3'    , 'f(3)',   'f(3)' ], # , 'f_oe' ],
         # JTAG
-        [ 'p_tck_0'    , 'tck',   'tck'], # 2nd clock
-        [ 'p_tms_0'    , 'tms',   'tms'],
-        [ 'p_tdo_0'    , 'tdo',   'tdo'],
-        [ 'p_tdi_0'    , 'tdi',   'tdi'],
+        [ 'p_jtag_tck'    , 'jtag_tck',   'jtag_tck'], # 2nd clock
+        [ 'p_jtag_tms'    , 'jtag_tms',   'jtag_tms'],
+        [ 'p_jtag_tdo'    , 'jtag_tdo',   'jtag_tdo'],
+        [ 'p_jtag_tdi'    , 'jtag_tdi',   'jtag_tdi'],
         ],
         'pads.south'      :
             [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0', 'p_a2', 'p_b3', ],

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index 33311d3325998d9e8ebf1ab20e922f7fe044b07d..bcf0965be949fbb568501bf12b0ce873aa4195f3 100644 (file)
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -20,10 +20,10 @@ class ADD(Elaboratable):
 
         # set up JTAG
         self.jtag = TAP(ir_width=4)
-        self.jtag.bus.tck.name = 'tck'
-        self.jtag.bus.tms.name = 'tms'
-        self.jtag.bus.tdo.name = 'tdo'
-        self.jtag.bus.tdi.name = 'tdi'
+        self.jtag.bus.tck.name = 'jtag_tck'
+        self.jtag.bus.tms.name = 'jtag_tms'
+        self.jtag.bus.tdo.name = 'jtag_tdo'
+        self.jtag.bus.tdi.name = 'jtag_tdi'
 
         # have to create at least one shift register
         self.sr = self.jtag.add_shiftreg(ircode=4, length=3)

diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py
index 7c24dff975879b181d0cd2ddb50cef26eb6b9429..5c739c21609f4b491bc380b6e925a4facc9bd6ea 100644 (file)
--- a/experiments10_verilog/coriolis2/settings.py
+++ b/experiments10_verilog/coriolis2/settings.py
@@ -35,7 +35,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()
-    env.setCLOCK( '^clk|^ck|^tck' )
+    env.setCLOCK( '^clk|^ck|^jtag_tck' )
     env.setPOWER( 'vdd' )
     env.setGROUND( 'vss' )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib',

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index addccdb56e795e5ec2741f7b971212ba21982449..dad7f430d91550a775c2270d15e0bbfe88909185 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -42,12 +42,12 @@ def scriptMain ( **kw ):
          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
          , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
          , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )
-         , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'      )
-         , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'      )
+         , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms'    , 'jtag_tms'      )
+         , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo'    , 'jtag_tdo'      )
          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
          , (IoPin.EAST , None, 'clk'  , 'clk'    , 'clk'      )
-         , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'      )
-         , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'      )
+         , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck'    , 'jtag_tck'      )
+         , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi'    , 'jtag_tdi'      )
          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
@@ -85,7 +85,7 @@ def scriptMain ( **kw ):
 
         rvalue = chipBuilder.doPnR()
         chipBuilder.save()
-        CRL.Gds.save(ls180Conf.chip)
+        CRL.Gds.save(adderConf.chip)
 
     except Exception, e:
         helpers.io.catch( e )