initial commit of sim state class

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
new file mode 100644 (file)
index 0000000..0520d16
--- /dev/null
+++ b/src/soc/simple/test/teststate.py
@@ -0,0 +1,11 @@
+class SimState:
+    def __init__(self, sim):
+        self.sim = sim
+
+    def get_intregs(self):
+        self.intregs = []
+        for i in range(32):
+            simregval = self.sim.gpr[i].asint()
+            self.intregs.append(simregval)
+
+# HDL class here with same functions