doh

diff --git a/src/ls2.py b/src/ls2.py
index 993186f3ee55afa643b55961c06c0db2a475a082..89d6c06b40565ae7a89166dcbe465c372848bc91 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -795,7 +795,7 @@ class DDR3SoC(SoC, Elaboratable):
         # and at the moment that's just UART tx/rx.
         ports = []
         ports += [self.uart.tx_o, self.uart.rx_i]
-        for hr in self.hyperramL
+        for hr in self.hyperram:
             ports += list(hr.ports())
         if hasattr(self, "ddrphy"):
             if hasattr(self.ddrphy, "pads"): # real PHY