beginning to add hyperram module

diff --git a/src/ls2.py b/src/ls2.py
index 3adbc73dcdf7e5267eb7b577865d2c29de05ddbd..2a3e819ffbe4f1822b745453860192974450d1ba 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -16,6 +16,7 @@ from nmigen_soc import wishbone, memory
 from nmigen_soc.memory import MemoryMap
 
 from nmigen_stdio.serial import AsyncSerial
+from nmigen_boards.resources.memory import HyperRAMResource
 
 from lambdasoc.periph.intc import GenericInterruptController
 from lambdasoc.periph.sram import SRAMPeripheral
@@ -221,11 +222,13 @@ class DDR3SoC(SoC, Elaboratable):
     def __init__(self, *,
                  fpga,
                  dram_cls,
-                 uart_pins, spi_0_pins, ddr_pins,
-                 ddrphy_addr, dramcore_addr,
-                 ddr_addr, fw_addr=0x0000_0000,
+                 uart_pins, spi_0_pins,
+                 ddr_pins, ddrphy_addr, dramcore_addr, ddr_addr,
+                 fw_addr=0x0000_0000,
                  firmware=None,
                  spi0_addr, spi0_cfg_addr,
+                 hyperram_addr=None,
+                 hyperram_pinset=None,
                  clk_freq=50e6,
                  add_cpu=True):
 
@@ -370,7 +373,8 @@ class DDR3SoC(SoC, Elaboratable):
             self._decoder.add(self.drambone.bus, addr=ddr_addr)
 
         # SPI controller
-        if spi_0_pins is not None or fpga == 'sim':
+        if spi_0_pins is not None and fpga in ['sim',
+                                             'rcs_arctic_tern_bmc_card']:
             # The Lattice ECP5 devices require special handling on the
             # dedicated SPI clock line, which is shared with the internal
             # SPI controller used for FPGA bitstream loading.
@@ -393,6 +397,9 @@ class DDR3SoC(SoC, Elaboratable):
             self._decoder.add(self.spi0.bus, addr=spi0_addr)
             self._decoder.add(self.spi0.cfg_bus, addr=spi0_cfg_addr)
 
+        # HyperRAM modules *plural*. Assumes using a Quad PMOD by Piotr
+        # Esden, sold by 1bitsquared
+
         self.memory_map = self._decoder.bus.memory_map
 
         self.clk_freq = clk_freq
@@ -589,6 +596,16 @@ if __name__ == "__main__":
                                         dir={"dq":"io", "cs_n":"o", "clk":"o"},
                                         xdr={"dq": 1, "cs_n": 1, "clk": 0})
 
+    # Get HyperRAM pinsets, there are multiple of these!
+    hyperram_pinset = None
+    if platform is not None and fpga in ['versa_ecp5']:
+        hyperram_ios = HyperRAMResources(cs_n="B1",
+                                         dq="D0 D1 D2 D3 D4 D7 D6 D7",
+                                         rwds="B2", rst_n="B3", clk_p="B4",
+                                         attrs=IOStandard("LVCMOS33"))
+        self.platform.add_extension(hyperram_ios)
+        hyperram_pinset = self.platform.request("hyperram")
+
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
                   # check microwatt_soc.h for these
@@ -597,11 +614,13 @@ if __name__ == "__main__":
                   ddr_addr=0x40000000,      # DRAM_BASE
                   spi0_addr=0x10000000,     # SPI0_BASE
                   spi0_cfg_addr=0xc0003000, # SPI0_CTRL_BASE
+                  hyperram_addr=0xa0000000, # HYPERRAM_BASE
                   fw_addr=fw_addr,
                   #fw_addr=None,
                   ddr_pins=ddr_pins,
                   uart_pins=uart_pins,
                   spi_0_pins=spi_0_pins,
+                  hyperram_pinset=hyperram_pinset,
                   firmware=firmware,
                   clk_freq=clk_freq,
                   add_cpu=True)