Management of SRAMs block at Coriolis devel.

Sub block instanciating the real SRAM are added on the fly to the
Yosys blackboxes spblock512w64b8w_X. Must be done *before* ls180
loading.

diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py
index c3b2d13bbdcddddcfdb99d1fdbb7826ca01d57d7..cd266380f3786fcb1481f05a7e3aa73e1e33d1c9 100644 (file)
--- a/experiments9/tsmc_c018/coriolis2/settings.py
+++ b/experiments9/tsmc_c018/coriolis2/settings.py
@@ -1,5 +1,6 @@
 # -*- Mode:Python -*-
 
+from   __future__ import print_function
 import os
 import socket
 import helpers
@@ -12,14 +13,15 @@ if not NdaDirectory:
     if hostname.startswith('lepka'):
         NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno'
         if not os.path.isdir(NdaDirectory):
-            print '[ERROR] You forgot to mount the NDA encrypted directory, stupid!'
+            print( '[ERROR] You forgot to mount the NDA encrypted directory, stupid!' )
     else:
         NdaDirectory = '/users/soft/techno/techno'
 helpers.setNdaTopDir( NdaDirectory )
 
 import Cfg
-from   CRL     import AllianceFramework
-from   helpers import overlay, l, u, n
+from   Hurricane import DataBase, Cell, Instance, Net
+from   CRL       import AllianceFramework
+from   helpers   import overlay, l, u, n
 from   NDA.node180.tsmc_c018 import techno, FlexLib, LibreSOCIO, LibreSOCMem, pll
 
 techno.setup()
@@ -28,6 +30,49 @@ LibreSOCIO.setup()
 LibreSOCMem.setup()
 pll.setup()
 
+
+db = DataBase.getDB()
+af = AllianceFramework.get()
+
+
+def createSramBlackbox ():
+    global db, af
+    print( '  o  Creating SRAM blackboxes for "ls180" design.' )
+    rootlib  = db.getRootLibrary()
+    lib      = rootlib.getLibrary( 'LibreSOCMem' )
+    sramName = 'spblock_512w64b8w'
+    sram     = lib.getCell( sramName )
+    if not sram:
+        raise ErrorMessage( 1, 'settings.createSramBlocks(): SRAM Cell "{}" not found.' \
+                               .format(sramName) )
+    sram.setAbstractedSupply( True )
+    blackboxeNames = [ 'spblock512w64b8w_0'
+                     , 'spblock512w64b8w_1'
+                     , 'spblock512w64b8w_2'
+                     , 'spblock512w64b8w_3'
+                     ]
+    for blackboxName in blackboxeNames:
+        cell     = Cell.create( lib, blackboxName )
+        instance = Instance.create( cell, 'real_sram', sram )
+        state    = af.getCatalog().getState( blackboxName, True )
+        state.setCell( cell )
+        state.setLogical( True )
+        state.setInMemory( True )
+        print( '     - {}.'.format(cell) )
+        for masterNet in sram.getNets():
+            if not masterNet.isExternal():
+                continue
+            net = Net.create( cell, masterNet.getName() )
+            net.setDirection( masterNet.getDirection() )
+            net.setType( masterNet.getType() )
+            net.setExternal( True )
+            net.setGlobal( masterNet.isGlobal() )
+            if masterNet.isSupply():
+                continue
+            plug = instance.getPlug( masterNet )
+            plug.setNet( net )
+
+
 with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.misc.catchCore           = False
     cfg.misc.minTraceLevel       = 12300
@@ -41,6 +86,8 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.etesian.graphics         = 3
     cfg.etesian.spaceMargin      = 0.10
     cfg.katana.eventsLimit       = 4000000
-    af  = AllianceFramework.get()
     env = af.getEnvironment()
     env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
+
+with overlay.UpdateSession():
+    createSramBlackbox()

diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index d1389a0c529ff844fec2f2fc3af0eb0daed28c17..7c9573259767fe484019661b821d87eb8f26a520 100644 (file)
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -168,8 +168,8 @@ def scriptMain (**kw):
                   , (IoPin.NORTH, None, 'jtag_tdo'     , 'jtag_tdo'     , 'jtag_tdo' )
                   , (IoPin.NORTH, None, 'jtag_tck'     , 'jtag_tck'     , 'jtag_tck' )
                   , (IoPin.NORTH, None, 'sys_clk'      , 'sys_clk'      , 'sys_clk' )
-                  , (IoPin.NORTH, None, 'sys_pll_18_o' , 'sys_pll_18_o' , 'sys_pll_18_o' )
-                  , (IoPin.NORTH, None, 'sys_pll_lck_o', 'sys_pll_lck_o', 'sys_pll_lck_o' )
+                  , (IoPin.NORTH, None, 'sys_pll_testout_o' , 'sys_pll_testout_o' , 'sys_pll_testout_o' )
+                  , (IoPin.NORTH, None, 'sys_pll_vco_o', 'sys_pll_vco_o', 'sys_pll_vco_o' )
                   ]
     ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'sys_clksel_i{}', 'sys_clksel_i({})', 'sys_clksel_i({})'), 2 )
     ioPadsSpec += doIoPowerCap( IoPin.NORTH|IoPin.A_END )
@@ -226,10 +226,17 @@ def scriptMain (**kw):
         ls180Conf.coreSize = (coreSizeX, coreSizeY)
         ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) )
 
-        with UpdateSession():
-            sliceHeight = ls180Conf.sliceHeight
-            coreAb      = Box( 0, 0, coreSizeX, coreSizeY )
-            rsetAbutmentBox( cell, coreAb )
+        #`tiId & sramId are dependent on Yosys. They need to be adjusted whenever
+        # the design changes.
+        tiId   = 12969
+        sramId = 3482
+        tiPath = 'subckt_{}_test_issuer.subckt_1_ti.'.format(tiId)
+        sramDatas \
+            = [ [tiPath+'subckt_{}_sram4k_0.subckt_152_spblock512w64b8w_0.real_sram'.format(sramId  ), -2]
+              , [tiPath+'subckt_{}_sram4k_1.subckt_152_spblock512w64b8w_1.real_sram'.format(sramId+1),  3]
+              , [tiPath+'subckt_{}_sram4k_2.subckt_152_spblock512w64b8w_2.real_sram'.format(sramId+2),  2]
+              , [tiPath+'subckt_{}_sram4k_3.subckt_152_spblock512w64b8w_3.real_sram'.format(sramId+3),  3]
+              ]
 
         ls180ToChip = CoreToChip( ls180Conf )
         ls180ToChip.buildChip()
@@ -237,35 +244,13 @@ def scriptMain (**kw):
         chipBuilder.doChipFloorplan()
 
         with UpdateSession():
-            # Thoses ids are dependent on Yosys. They need to be adjusted whenever
-            # the design changes.
-            #tiId   = 38695
-            #tiId   = 38381
-            #tiId   = 10863
-            tiId   = 12974
-            #sramId = 3695
-            #sramId = 3300
-            #sramId = 3301
-            sramId = 3481
-            tiPath = 'subckt_{}_test_issuer.subckt_1_ti.'.format(tiId)
-            sramDatas \
-                = [ (tiPath+'subckt_{}_sram4k_0.subckt_152_spblock_512w64b8w'.format(sramId)  , -2)
-                  , (tiPath+'subckt_{}_sram4k_1.subckt_152_spblock_512w64b8w'.format(sramId+1),  3)
-                  , (tiPath+'subckt_{}_sram4k_2.subckt_152_spblock_512w64b8w'.format(sramId+2),  2)
-                  , (tiPath+'subckt_{}_sram4k_3.subckt_152_spblock_512w64b8w'.format(sramId+3),  3)
-                  ]
-            sram = DataBase.getDB().getCell( 'spblock_512w64b8w' )
-            if not sram:
-                raise ErrorMessage( 1, 'SRAM instance "{}" not found.'.format(sramDatas[i][0]) )
-            sram.setAbstractedSupply( True )
-            sramAb = sram.getAbutmentBox()
+            sram        = DataBase.getDB().getCell( 'spblock_512w64b8w' )
             sramAb      = sram.getAbutmentBox()
             coreAb      = cell.getAbutmentBox()
             sliceHeight = chipBuilder.conf.sliceHeight
             sliceStep   = chipBuilder.conf.sliceStep
             originX     = coreAb.getXMin() + sramDatas[0][1]*chipBuilder.conf.sliceStep
             for i in range(len(sramDatas)):
-                sram = rgetInstance( cell, sramDatas[i][0] )
                 chipBuilder.placeMacro \
                     ( sramDatas[i][0]
                     , Transformation( originX