remove stall from WBASyncBridges on master side

leave them on slave side and fake them up (stb&~ack)

diff --git a/src/ls2.py b/src/ls2.py
index 1c0f3fe29e146d89e8a283082422807bca2ab48c..ec81aa3570e8600be09903abbac6b5c0490b7142 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -489,8 +489,7 @@ class DDR3SoC(SoC, Elaboratable):
                                  slave_clock_domain="dramsync",
                                  address_width=self.ddrphy.bus.addr_width,
                                  data_width=self.ddrphy.bus.data_width,
-                                 granularity=self.ddrphy.bus.granularity,
-                                 master_features={'stall'})
+                                 granularity=self.ddrphy.bus.granularity)
             self.ddrphy_async_br = pabr
 
             # Set up Wishbone asynchronous bridge
@@ -507,8 +506,7 @@ class DDR3SoC(SoC, Elaboratable):
                                 slave_clock_domain="dramsync",
                                 address_width=self.dramcore.bus.addr_width,
                                 data_width=self.dramcore.bus.data_width,
-                                granularity=self.dramcore.bus.granularity,
-                                master_features={'stall'})
+                                granularity=self.dramcore.bus.granularity)
             self.dramcore_async_br = dac
 
             # Set up Wishbone asynchronous bridge
@@ -525,8 +523,7 @@ class DDR3SoC(SoC, Elaboratable):
                                 slave_clock_domain="dramsync",
                                 address_width=self.drambone.bus.addr_width,
                                 data_width=self.drambone.bus.data_width,
-                                granularity=self.drambone.bus.granularity,
-                                master_features={'stall'})
+                                granularity=self.drambone.bus.granularity)
             self.drambone_async_br = bab
 
         if ddr_pins is not None:
@@ -860,7 +857,7 @@ def build_platform(fpga, firmware):
         dram_clk_freq = 100e6
     if fpga == 'versa_ecp5':
         clk_freq = 40e6 # crank right down to timing threshold
-        dram_clk_freq = 100e6
+        dram_clk_freq = 55e6
     if fpga == 'versa_ecp5_85':
         # 50MHz works.  100MHz works.  55MHz does NOT work.
         # Stick with multiples of 50MHz...
@@ -909,7 +906,7 @@ def build_platform(fpga, firmware):
 
     # Get SPI resource pins
     spi_0_pins = None
-    if platform is not None and \
+    if False and platform is not None and \
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # Override here to get FlashResource out of the way and enable Tercel
         # direct access to the SPI flash.