import unittest
from nmigen import Signal, Module
-from nmigen.hdl.ast import Cover
+from nmigen.hdl.ast import Cover, Const
from nmutil.formaltest import FHDLTestCase
from nmutil.singlepipe import ControlBase
cnt_masked_read = []
for i in range(dut.n_src):
cnt = Signal(4, name="cnt_masked_read_%d" % i)
- m.d.sync += cnt.eq(cnt + (do_issue & dut.rdmaskn[i]))
+ if i == 0:
+ extra = dut.oper_i.zero_a
+ elif i == 1:
+ extra = dut.oper_i.imm_data.ok
+ else:
+ extra = Const(0, 1)
+ m.d.sync += cnt.eq(cnt + (do_issue & (dut.rdmaskn[i] | extra)))
cnt_masked_read.append(cnt)
# Ask the formal engine to give an example