def __init__(self, n_units, mem, regwid=64, addrwid=48):
self.n_units = n_units
self.mem = mem
+ self.regwid = regwid
+ self.addrwid = addrwid
ul = []
for i in range(n_units):
ul.append(LDSTPort(i, regwid, addrwid))
self.dports = Array(ul)
+ def truncaddr(self, addr):
+ """truncates the address to the top bits of the memory granularity
+ """
+ nbits = log2_int(self.mem.regwid)
+ return addr[nbits:]
+
def elaborate(self, platform):
m = Module()
comb, sync = m.d.comb, m.d.sync