projects / soc.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 52a5fd4)
fix up pr/dr/sf in PortInterfaceBase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 13 Dec 2021 13:08:53 +0000 (13:08 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 13 Dec 2021 13:08:53 +0000 (13:08 +0000)
src/soc/experiment/pimem.py patch | blob | history

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 58f6c4e82eac7137ffa18a4b6a873c9a9a72bcf8..52605a1452bc85602adc7e4844beaf186645b760 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -225,8 +225,8 @@ class PortInterfaceBase(Elaboratable):
         # TODO: construct an MSRspec here and pass it over in
         # self.set_rd_addr and set_wr_addr below rather than just pr
         pr = ~pi.priv_mode
-        dr = pi.virt_mode   # not yet used
-        sf = pi.mode_32bit   # not yet used
+        dr = pi.virt_mode
+        sf = ~pi.mode_32bit
         msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 
         # detect busy "edge"