use ComMULOpSubset in mul pipeline

diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py
new file mode 100644 (file)
index 0000000..8554c53
--- /dev/null
+++ b/src/soc/fu/mul/mul_input_record.py
@@ -0,0 +1,60 @@
+from nmigen.hdl.rec import Record, Layout
+
+from soc.decoder.power_enums import InternalOp, Function, CryIn
+
+
+class CompMULOpSubset(Record):
+    """CompMULOpSubset
+
+    a copy of the relevant subset information from Decode2Execute1Type
+    needed for MUL operations.  use with eq_from_execute1 (below) to
+    grab subsets.
+    """
+    def __init__(self, name=None):
+        layout = (('insn_type', InternalOp),
+                  ('fn_unit', Function),
+                  ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
+                  ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
+                  ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
+                  ('invert_a', 1),
+                  ('zero_a', 1),
+                  ('invert_out', 1),
+                  ('write_cr0', 1),
+                  ('input_carry', CryIn),
+                  ('output_carry', 1),
+                  ('is_32bit', 1),
+                  ('is_signed', 1),
+                  ('insn', 32),
+                  )
+
+        Record.__init__(self, Layout(layout), name=name)
+
+        # grrr.  Record does not have kwargs
+        self.insn_type.reset_less = True
+        self.fn_unit.reset_less = True
+        self.zero_a.reset_less = True
+        self.invert_a.reset_less = True
+        self.invert_out.reset_less = True
+        self.input_carry.reset_less = True
+        self.output_carry.reset_less = True
+        self.is_32bit.reset_less = True
+        self.is_signed.reset_less = True
+
+    def eq_from_execute1(self, other):
+        """ use this to copy in from Decode2Execute1Type
+        """
+        res = []
+        for fname, sig in self.fields.items():
+            eqfrom = other.do.fields[fname]
+            res.append(sig.eq(eqfrom))
+        return res
+
+    def ports(self):
+        return [self.insn_type,
+                self.invert_a,
+                self.invert_out,
+                self.input_carry,
+                self.output_carry,
+                self.is_32bit,
+                self.is_signed,
+        ]

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index 1b37b484b7e27a3e43fb8c37af3281269d8fcf81..38741f61bab416c2d2bd10388aa58b47280a7424 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -1,4 +1,4 @@
-from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.mul.mul_input_record import CompMULOpSubset
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from soc.fu.alu.pipe_data import ALUOutputData, ALUInputData
 from nmigen import Signal
@@ -29,4 +29,4 @@ class MulOutputData(IntegerData):
 
 class MulPipeSpec(CommonPipeSpec):
     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
-    opsubsetkls = CompALUOpSubset
+    opsubsetkls = CompMULOpSubset