radeonsi: move index buffer flushing into a non-upload indexed case

The other codepaths don't need this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index d4533093e46b40debe6c7065c6f2f2d8d8d9ee08..e341f33fb1acdb19ab63443a5572d494c347373a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1086,16 +1086,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                                return;
                        /* info->start will be added by the drawing code */
                        ib.offset -= start_offset;
+               } else if (sctx->b.chip_class <= CIK &&
+                          r600_resource(ib.buffer)->TC_L2_dirty) {
+                       /* VI reads index buffers through TC L2, so it doesn't
+                        * need this. */
+                       sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
+                       r600_resource(ib.buffer)->TC_L2_dirty = false;
                }
        }
 
-       /* VI reads index buffers through TC L2. */
-       if (info->indexed && sctx->b.chip_class <= CIK &&
-           r600_resource(ib.buffer)->TC_L2_dirty) {
-               sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
-               r600_resource(ib.buffer)->TC_L2_dirty = false;
-       }
-
        if (info->indirect) {
                /* Add the buffer size for memory checking in need_cs_space. */
                r600_context_add_resource_size(ctx, info->indirect);