got test_issuer operational on one unit test

however needs further investigation

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 40592061a3ff45133a864da8aa1c556abc5374e0..1159a85da2feb8937e820ce1226823109dd273a3 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -25,12 +25,12 @@ from soc.fu.compunits.test.test_compunit import (setup_test_memory,
                                                  check_sim_memory)
 
 # test with ALU data and Logical data
-from soc.fu.alu.test.test_pipe_caller import ALUTestCase
+#from soc.fu.alu.test.test_pipe_caller import ALUTestCase
 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
-#from soc.fu.spr.test.test_pipe_caller import SPRTestCase
+from soc.fu.spr.test.test_pipe_caller import SPRTestCase
 #from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 #from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
 #from soc.simulator.test_helloworld_sim import HelloTestCases
@@ -100,6 +100,7 @@ class TestRunner(FHDLTestCase):
             for test in self.test_data:
 
                 # get core going
+                yield core.bigendian_i.eq(1)
                 yield core.core_start_i.eq(1)
                 yield
                 yield core.core_start_i.eq(0)
@@ -146,8 +147,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
                     # wait until executed
-                    #yield from wait_for_busy_hi(core)
-                    yield
+                    yield from wait_for_busy_hi(core)
                     yield from wait_for_busy_clear(core)
 
                     terminated = yield core.core_terminated_o
@@ -186,9 +186,9 @@ if __name__ == "__main__":
     #suite.addTest(TestRunner(CRTestCase.test_data))
     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
     #suite.addTest(TestRunner(LogicalTestCase.test_data))
-    suite.addTest(TestRunner(ALUTestCase.test_data))
+    #suite.addTest(TestRunner(ALUTestCase.test_data))
     #suite.addTest(TestRunner(BranchTestCase.test_data))
-    #suite.addTest(TestRunner(SPRTestCase.test_data))
+    suite.addTest(TestRunner(SPRTestCase.test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)