add hyperram iverilog runner including s27kl0641.v model

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 16de7a8e5bd2f04ba68aadd87d9f3d2ad4e4cb56..044283be4c21520c24812ceca065fe4d9711233d 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -66,16 +66,19 @@ int main(void) {
        console_init();
        //puts("Firmware launched...\n");
 
-       puts("fw..");
+       //puts("fw..");
 #if 1
        volatile uint32_t *hyperram = (uint32_t*)0xa0000000;
+    writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
+    tmp = readl((unsigned long)&(hyperram[0]));
+    return 0;
     while (1) {
         unsigned char c = getchar();
         putchar(c);
         if (c == 13) { // if CR send LF
 
             // quick write/read
-            writel(0xDEAF0000, (unsigned long)&(hyperram[0]));
+            writel(0xDEAF0123, (unsigned long)&(hyperram[0]));
             tmp = readl((unsigned long)&(hyperram[0]));
             puts("read ");
             uart_writeuint32(tmp);

diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
new file mode 100755 (executable)
index 0000000..02e4389
--- /dev/null
+++ b/runsimsoc_hyperram.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+set -e
+
+LIB_DIR=./src/ecp5u
+
+HYPERRAM_DIR=./s27kl0641/model
+
+# create the build_simsoc/top.il file with firmware baked-in
+python3 src/ls2.py isim ./coldboot/coldboot.bin
+
+# do some voodoo magic to get icarus to be happy with the ilang file
+yosys simsoc.ys
+
+# fix a bug in Lattice ECP5 models
+cp ${LIB_DIR}/DDRDLLA.v DDRDLLA.v
+patch DDRDLLA.v < DDRDLLA.patch
+
+# string together the icarus verilog files and start runnin
+iverilog -Wall -g2012 -s simsoctb -o simsoc \
+        src/simsoctb.v ./top.v \
+    ${HYPERRAM_DIR}/s27kl0641.v \
+    ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v \
+    ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
+       ${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v \
+    ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v \
+    ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
+       ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v \
+    ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v \
+    ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \
+    DDRDLLA.v \
+       ${LIB_DIR}/CLKDIVF.v
+vvp -n simsoc -fst-speed

diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v
new file mode 100644 (file)
index 0000000..be28bd2
--- /dev/null
+++ b/src/simsoc_hyperram_tb.v
@@ -0,0 +1,134 @@
+// Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
+// Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+`timescale 1 ns / 1 ns
+
+module simsoctb;
+  // GSR & PUR init requires for Lattice models
+  GSR GSR_INST (
+    .GSR(1'b1)
+  );
+  PUR PUR_INST (
+    .PUR (1'b1)
+  );
+
+  reg clkin;
+  wire sync;
+  wire sync2x;
+  wire dramsync;
+  wire init;
+
+  // Generate 100 Mhz clock
+  always 
+    begin
+      clkin = 1;
+      #5;
+      clkin = 0;
+      #5;
+    end
+
+    // Outputs
+    wire o_csn0;
+    wire o_clk;
+    wire o_resetn;
+
+    // Bidirs
+    wire [7:0] io_dq;
+    wire io_rwds;
+
+s27kl0641
+    #(
+    .TimingModel("S27KL0641DABHI000"))
+    hyperram (
+    .DQ7(io_dq[7]),
+    .DQ6(io_dq[6]),
+    .DQ5(io_dq[5]),
+    .DQ4(io_dq[4]),
+    .DQ3(io_dq[3]),
+    .DQ2(io_dq[2]),
+    .DQ1(io_dq[1]),
+    .DQ0(io_dq[0]),
+    .RWDS(io_rwds),
+    .CSNeg(o_csn0),
+    .CK(o_clk),
+    .RESETNeg(o_resetn)
+    );
+
+  // uart, LEDs, switches
+  wire uart_tx ;
+  reg uart_rx = 0;
+  wire led_0;
+  wire led_1;
+  wire led_2;
+  wire led_3;
+  wire led_4;
+  wire led_5;
+  wire led_6;
+  wire led_7;
+  reg switch_0 = 0;
+  reg switch_1 = 0;
+  reg switch_2 = 0;
+  reg switch_3 = 0;
+  reg switch_4 = 0;
+  reg switch_5 = 0;
+  reg switch_6 = 0;
+  reg switch_7 = 0;
+
+  //defparam ram_chip.
+  
+  top simsoctop (
+    // hyperram
+    .hyperram_0__cs_n__io(o_csn0), 
+    .hyperram_0__rst_n__io(o_resetn), 
+    .hyperram_0__rwds__io(io_rwds), 
+    .hyperram_0__ck__io(o_clk), 
+    .hyperram_0__dq__io(io_dq),
+    // uart
+    .uart_0__rx__io(uart_rx),
+    .uart_0__tx__io(uart_tx),
+    // led
+    .led_0__io(led_0),
+    .led_1__io(led_1),
+    .led_2__io(led_2),
+    .led_3__io(led_3),
+    .led_4__io(led_4),
+    .led_5__io(led_5),
+    .led_6__io(led_6),
+    .led_7__io(led_7),
+    // switches
+    .switch_0__io(switch_0),
+    .switch_1__io(switch_1),
+    .switch_2__io(switch_2),
+    .switch_3__io(switch_3),
+    .switch_4__io(switch_4),
+    .switch_5__io(switch_5),
+    .switch_6__io(switch_6),
+    .switch_7__io(switch_7),
+    // clock/reset
+    .clk100_0__p(clkin),
+    .rst_0__io(1'b0)
+  );
+
+  initial
+    begin
+      $dumpfile("simsoc_hyperram.fst");
+      $dumpvars(0, clkin);
+      $dumpvars(0, o_resetn);
+      $dumpvars(0, o_csn0);
+      $dumpvars(0, io_rwds);
+      $dumpvars(0, io_dq);
+      $dumpvars(0, uart_tx);
+      $dumpvars(0, uart_rx);
+      $dumpvars(0, simsoctop);
+      $dumpvars(0, ram_chip);
+    end
+
+  initial
+    begin
+      // run for a set time period then exit
+      #120000000;
+
+      $finish;
+    end
+
+endmodule