classic wishbone mode: must not do ack if already acked

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index 994f962647e23f5726a3001b9e6b1da1da1f47dd..25f2da74c3bf033235ec8e5e1e371441076305e7 100644 (file)
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -59,7 +59,8 @@ class SPBlock512W64B8W(Elaboratable):
         with m.If(self.enable): # in case of layout problems
             # wishbone is active if cyc and stb set
             wb_active = Signal()
-            m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb)
+            m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb &
+                                     ~self.bus.ack)
 
             # generate ack (no "pipeline" mode here)
             m.d.sync += self.bus.ack.eq(wb_active)