remove unneeded code

diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py
index 1bf971e754145684f1321cfdfec4731d5754dc1b..bc60a55a9ce4db149b050635d180e6d9faac1702 100644 (file)
--- a/src/ieee754/fpcommon/getop.py
+++ b/src/ieee754/fpcommon/getop.py
@@ -2,19 +2,14 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
+from nmigen import Module, Signal, Elaboratable
 from nmigen.lib.coding import PriorityEncoder
 from nmigen.cli import main, verilog
 from math import log
 
-from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, Overflow, FPBase, FPNumBase
-from ieee754.fpcommon.fpbase import MultiShiftRMerge, Trigger
-from nmutil.singlepipe import (ControlBase, StageChain,
-                        PassThroughStage, PrevControl)
-from nmutil.multipipe import CombMuxOutPipe
-from nmutil.multipipe import PriorityCombMuxInPipe
+from ieee754.fpcommon.fpbase import FPOpIn, FPBase, FPNumBase
+from nmutil.singlepipe import PrevControl
 
-from ieee754.fpcommon.fpbase import FPState
 from nmutil import nmoperator
 
 
@@ -30,7 +25,6 @@ class FPGetOpMod(Elaboratable):
         m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
                                        (self.in_op.valid_i_test))
         m.submodules.get_op_in = self.in_op
-        #m.submodules.get_op_out = self.out_op
         with m.If(self.out_decode):
             m.d.comb += [
                 self.out_op.eq(self.in_op.v),
@@ -38,36 +32,6 @@ class FPGetOpMod(Elaboratable):
         return m
 
 
-class FPGetOp(FPState):
-    """ gets operand
-    """
-
-    def __init__(self, in_state, out_state, in_op, width):
-        FPState.__init__(self, in_state)
-        self.out_state = out_state
-        self.mod = FPGetOpMod(width)
-        self.in_op = in_op
-        self.out_op = Signal(width)
-        self.out_decode = Signal(reset_less=True)
-
-    def setup(self, m, in_op):
-        """ links module to inputs and outputs
-        """
-        setattr(m.submodules, self.state_from, self.mod)
-        m.d.comb += nmoperator.eq(self.mod.in_op, in_op)
-        m.d.comb += self.out_decode.eq(self.mod.out_decode)
-
-    def action(self, m):
-        with m.If(self.out_decode):
-            m.next = self.out_state
-            m.d.sync += [
-                self.in_op.ready_o.eq(0),
-                self.out_op.eq(self.mod.out_op)
-            ]
-        with m.Else():
-            m.d.sync += self.in_op.ready_o.eq(1)
-
-
 class FPNumBase2Ops:
 
     def __init__(self, width, id_wid, m_extra=True):
@@ -170,50 +134,3 @@ class FPGet2OpMod(PrevControl):
         return m
 
 
-class FPGet2Op(FPState):
-    """ gets operands
-    """
-
-    def __init__(self, in_state, out_state, width, id_wid, op_wid=None):
-        FPState.__init__(self, in_state)
-        self.out_state = out_state
-        self.mod = FPGet2OpMod(width, id_wid, op_wid)
-        self.o = self.ospec()
-        self.in_stb = Signal(reset_less=True)
-        self.out_ack = Signal(reset_less=True)
-        self.out_decode = Signal(reset_less=True)
-
-    def ispec(self):
-        return self.mod.ispec()
-
-    def ospec(self):
-        return self.mod.ospec()
-
-    def trigger_setup(self, m, in_stb, in_ack):
-        """ links stb/ack
-        """
-        m.d.comb += self.mod.valid_i.eq(in_stb)
-        m.d.comb += in_ack.eq(self.mod.ready_o)
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.get_ops = self.mod
-        m.d.comb += self.mod.i.eq(i)
-        m.d.comb += self.out_ack.eq(self.mod.ready_o)
-        m.d.comb += self.out_decode.eq(self.mod.trigger)
-
-    def process(self, i):
-        return self.o
-
-    def action(self, m):
-        with m.If(self.out_decode):
-            m.next = self.out_state
-            m.d.sync += [
-                self.mod.ready_o.eq(0),
-                self.o.eq(self.mod.o),
-            ]
-        with m.Else():
-            m.d.sync += self.mod.ready_o.eq(1)
-
-