use CompBROpSubset and reduce it down in size (remove unneeded fields)

diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py
index d4f039cd300e1a5656eebbc798379cca3f1c2468..c7df72ca8bcab3eb0fe50f5a8371e88094e12f35 100644 (file)
--- a/src/soc/fu/branch/br_input_record.py
+++ b/src/soc/fu/branch/br_input_record.py
@@ -18,41 +18,19 @@ class CompBROpSubset(Record):
         layout = (('insn_type', InternalOp),
                   ('fn_unit', Function),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
-                   #'cr = Signal(32) # NO: this is from the CR SPR
-                    #'xerc = XerBits() # NO: this is from the XER SPR
                   ('lk', 1),
-                  ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
-                  ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
-                  ('invert_a', 1),
-                  ('invert_out', 1),
-                  ('input_carry', CryIn),
-                  ('output_carry', 1),
-                  ('input_cr', 1),
-                  ('output_cr', 1),
                   ('is_32bit', 1),
-                  ('is_signed', 1),
                   ('insn', 32),
-                  ('byte_reverse', 1),
-                  ('sign_extend', 1))
+                  )
 
         Record.__init__(self, Layout(layout), name=name)
 
         # grrr.  Record does not have kwargs
         self.insn_type.reset_less = True
         self.fn_unit.reset_less = True
-        #self.cr = Signal(32, reset_less = True
-        #self.xerc = XerBits(
         self.lk.reset_less = True
-        self.invert_a.reset_less = True
-        self.invert_out.reset_less = True
-        self.input_carry.reset_less = True
-        self.output_carry.reset_less = True
-        self.input_cr.reset_less = True
-        self.output_cr.reset_less = True
         self.is_32bit.reset_less = True
-        self.is_signed.reset_less = True
-        self.byte_reverse.reset_less = True
-        self.sign_extend.reset_less = True
+        self.insn.reset_less = True
 
     def eq_from_execute1(self, other):
         """ use this to copy in from Decode2Execute1Type
@@ -65,17 +43,8 @@ class CompBROpSubset(Record):
 
     def ports(self):
         return [self.insn_type,
-                #self.cr,
-                #self.xerc,
+                self.fn_unit,
                 self.lk,
-                self.invert_a,
-                self.invert_out,
-                self.input_carry,
-                self.output_carry,
-                self.input_cr,
-                self.output_cr,
                 self.is_32bit,
-                self.is_signed,
-                self.byte_reverse,
-                self.sign_extend,
+                self.insn,
         ]

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index ad12d56f988aa3e09b895fe7c092e6cc6da597d8..1f79a704a6dabc7dd65780b346cf3e2b842f0165 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -27,7 +27,7 @@ from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
+from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
 
 
 class BranchInputData(IntegerData):
@@ -89,7 +89,7 @@ class BranchOutputData(IntegerData):
                       self.nia.eq(i.nia)]
 
 
-# TODO: replace CompALUOpSubset with CompBranchOpSubset
+# TODO: replace CompALUOpSubset with CompBROpSubset
 class BranchPipeSpec(CommonPipeSpec):
     regspec = (BranchInputData.regspec, BranchOutputData.regspec)
-    opsubsetkls = CompALUOpSubset
+    opsubsetkls = CompBROpSubset