clear compalu data latch always on issue

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index c4dcfd15cd3ca999f1f9c0b8156130065d9622da..79d4ccd1698fada3cb4554b32cc4575c72777728 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -276,7 +276,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
             wrok.append(ok & self.busy_o)
             with m.If(alu_pulse):
                 m.d.sync += data_r.eq(lro)
-            with m.Elif(self.issue_i):
+            with m.If(self.issue_i):
                 m.d.sync += data_r.eq(0)
             drl.append(data_r)