move traptype to soc.consts

diff --git a/src/soc/consts.py b/src/soc/consts.py
index f29ddcfb0b70de1a5dc0b8bfa0d8e30ca92a0a84..ce877354dc3850f22016685a0d74919c45a41f40 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -27,3 +27,11 @@ class PI:
     TRAP  = (63 - 46)    # 1 if exception is "trap" type
     ADR   = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
 
+# see traptype (and trap main_stage.py)
+
+class TT:
+    FP = 1<<0
+    PRIV = 1<<1
+    TRAP = 1<<2
+    ADDR = 1<<3
+    ILLEG = 1<<4

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 5ae286e55cfd4b2005ada0c5e9bec51a95bd6ccb..9f46e3f032326922de9d2568797ca1dc73e18500 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -23,14 +23,8 @@ from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
 from soc.consts import MSR
 
 from soc.regfile.regfiles import FastRegs
+from soc.consts import TT
 
-# see traptype (and trap main_stage.py)
-
-TT_FP = 1<<0
-TT_PRIV = 1<<1
-TT_TRAP = 1<<2
-TT_ADDR = 1<<3
-TT_ILLEG = 1<<4
 
 def decode_spr_num(spr):
     return Cat(spr[5:10], spr[0:5])
@@ -682,7 +676,7 @@ class PowerDecode2(Elaboratable):
         # TODO: get msr, then can do privileged instruction
         with m.If(instr_is_priv(m, op.internal_op, e.do.insn) & msr[MSR.PR]):
             # privileged instruction trap
-            self.trap(m, TT_PRIV, 0x700)
+            self.trap(m, TT.PRIV, 0x700)
 
         # illegal instruction must redirect to trap. this is done by
         # *overwriting* the decoded instruction and starting again.
@@ -690,7 +684,7 @@ class PowerDecode2(Elaboratable):
         # just with different trapaddr and traptype)
         with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
             # illegal instruction trap
-            self.trap(m, TT_ILLEG, 0x700)
+            self.trap(m, TT.ILLEG, 0x700)
 
         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
         # Note: OP_SC could actually be modified to just be a trap

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 2444d7d543fefc49611689ff570d7362a321fcab..45038c2047c9b096cf167b7b361bd9c0935a96ef 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -19,9 +19,7 @@ from soc.decoder.power_enums import MicrOp
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR,
-                                        TT_ILLEG)
-from soc.consts import MSR, PI
+from soc.consts import MSR, PI, TT
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):
@@ -154,13 +152,13 @@ class TrapMainStage(PipeModBase):
                     with m.If(traptype == 0):
                         # say trap occurred (see 3.0B Book III 7.5.9)
                         comb += srr1_o.data[PI.TRAP].eq(1)
-                    with m.If(traptype & TT_PRIV):
+                    with m.If(traptype & TT.PRIV):
                         comb += srr1_o.data[PI.PRIV].eq(1)
-                    with m.If(traptype & TT_FP):
+                    with m.If(traptype & TT.FP):
                         comb += srr1_o.data[PI.FP].eq(1)
-                    with m.If(traptype & TT_ADDR):
+                    with m.If(traptype & TT.ADDR):
                         comb += srr1_o.data[PI.ADR].eq(1)
-                    with m.If(traptype & TT_ILLEG):
+                    with m.If(traptype & TT.ILLEG):
                         comb += srr1_o.data[PI.ILLEG].eq(1)
 
             # move to MSR