sigh, broken experiment10_verilog

diff --git a/experiments10_verilog/coriolis2/ioring.py b/experiments10_verilog/coriolis2/ioring.py
index 3842e0ed8c0e480a2e9e91ccfe773e9ef52adbef..920ee45f3f5c235b07b390f49918285daec833b5 100644 (file)
--- a/experiments10_verilog/coriolis2/ioring.py
+++ b/experiments10_verilog/coriolis2/ioring.py
@@ -23,21 +23,21 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
         [ 'p_f2'    , 'f(2)',   'f(2)' ], # , 'f_oe' ],
         [ 'p_f3'    , 'f(3)',   'f(3)' ], # , 'f_oe' ],
         # JTAG
-        [ 'p_tck_0'    , 'tck',   'tck'], # 2nd clock
-        [ 'p_tms_0'    , 'tms',   'tms'],
-        [ 'p_tdo_0'    , 'tdo',   'tdo'],
-        [ 'p_tdi_0'    , 'tdi',   'tdi'],
+        [ 'p_jtag_tck_0'    , 'tck',   'tck'], # 2nd clock
+        [ 'p_jtag_tms_0'    , 'tms',   'tms'],
+        [ 'p_jtag_tdo_0'    , 'tdo',   'tdo'],
+        [ 'p_jtag_tdi_0'    , 'tdi',   'tdi'],
         ],
         'pads.south'      :
-            [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0', 'p_a2', 'p_b3', ],
+            [ 'p_a1', 'iopower_0', 'power_0' , 'p_a0', 'p_a2', 'p_b3', ],
        'pads.east'       :
-            [ 'p_tck_0', # 2nd clock
-                'p_tms_0', 'p_tdo_0', 'p_tdi_0',
+            [ 'p_jtag_tck_0', # 2nd clock
+                'p_jtag_tms_0', 'p_jtag_tdo_0', 'p_jtag_tdi_0',
                 'p_b2'       ],
        'pads.north'      :
-            [ 'p_b1', 'p_vddeck_0', 'p_b0', 'p_vsseck_0', 'rst' ],
+            [ 'p_b1', 'ioground_0', 'p_b0', 'ground_0', 'p_sys_rst' ],
        'pads.west'       :
-            [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1' , 'p_f0', 'p_a3' ],
+            [ 'p_f3', 'p_f2'       , 'p_sys_clk_0', 'p_f1' , 'p_f0', 'p_a3' ],
        'core.size'       : ( l( 1200), l( 1200) ),
        'chip.size'       : ( l(3200), l(3200) ),
        'pads.useCoreSize'  : True,

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index e036f39b8770ae370090f37fa5efaf64ad46f907..26df5bd68bf7d79ad4e7265c7ea871904f3ab255 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -27,8 +27,6 @@ def scriptMain ( **kw ):
     rvalue = True
     try:
         helpers.setTraceLevel( 550 )
-        usePadsPosition = True
-        buildChip       = True
         cell, editor = plugins.kwParseMain( **kw )
         cell = af.getCell( 'add', CRL.Catalog.State.Logical )
         if cell is None:
@@ -81,10 +79,14 @@ def scriptMain ( **kw ):
         adderConf.chipSize = ( l(5900), l(5900) )
         adderToChip = CoreToChip( adderConf )
         adderToChip.buildChip()
+
         chipBuilder = Chip( adderConf )
         chipBuilder.doChipFloorplan()
+
         rvalue = chipBuilder.doPnR()
         chipBuilder.save()
+        CRL.Gds.save(ls180Conf.chip)
+
     except Exception, e:
         helpers.io.catch( e )
         rvalue = False