dewildcardify unitsg

diff --git a/src/soc/minerva/units/adder.py b/src/soc/minerva/units/adder.py
index 2971d98406da2bb5e490ae1f7ad113a5126b80de..eabdc6c2237a43713e2da9695a7b31efba1bcb02 100644 (file)
--- a/src/soc/minerva/units/adder.py
+++ b/src/soc/minerva/units/adder.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Cat
 
 
 __all__ = ["Adder"]

diff --git a/src/soc/minerva/units/compare.py b/src/soc/minerva/units/compare.py
index b11cdfe174f0c40f604923dba3b8047bb692b6c1..b8ba21715e1b8c59b86eb81afca2d4fa95514a84 100644 (file)
--- a/src/soc/minerva/units/compare.py
+++ b/src/soc/minerva/units/compare.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal
 
 from ..isa import Funct3
 

diff --git a/src/soc/minerva/units/decoder.py b/src/soc/minerva/units/decoder.py
index 0c75d503fa9db711de13ac31285620177987da64..7975d2d6ad81a911f087147f0fb18114684044ab 100644 (file)
--- a/src/soc/minerva/units/decoder.py
+++ b/src/soc/minerva/units/decoder.py
@@ -2,7 +2,7 @@ from functools import reduce
 from itertools import starmap
 from operator import or_
 
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Cat
 
 from ..isa import Opcode, Funct3, Funct7, Funct12
 

diff --git a/src/soc/minerva/units/divider.py b/src/soc/minerva/units/divider.py
index 6a98927c27f60ba3923be4ce92d7d7b383a8240c..fcc0a795ef0cbfc7ec984a268f5b4827061a2162 100644 (file)
--- a/src/soc/minerva/units/divider.py
+++ b/src/soc/minerva/units/divider.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Signal, Mux, Cat
 
 from ..isa import Funct3
 

diff --git a/src/soc/minerva/units/exception.py b/src/soc/minerva/units/exception.py
index 0d66b47e0fb9b210cd3a2877cc3f87af3e556017..1bee8402ddd23f201f5ad9100b91722096fb967c 100644 (file)
--- a/src/soc/minerva/units/exception.py
+++ b/src/soc/minerva/units/exception.py
@@ -1,8 +1,11 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal
 from nmigen.lib.coding import PriorityEncoder
 
-from ..csr import *
-from ..isa import *
+from ..csr import AutoCSR, CSR
+from ..isa import (Cause,
+                   mstatus_layout, misa_layout, mie_layout,
+                   mtvec_layout, flat_layout, mepc_layout, mcause_layout,
+                   flat_layout, mip_layout, flat_layout)
 
 
 __all__ = ["ExceptionUnit"]