write out data only on go_write

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index 5754da5be82776c8753f273a1c0e8a2089f613c4..18acbff814cc2d2796d89f4d968bb036633747ea 100644 (file)
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -214,8 +214,8 @@ class LDSTCompUnit(Elaboratable):
             with m.If(~self.alu.p_ready_o):          # no ACK yet
                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 
-        # put the register directly onto the output bus
-        with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)):
+        # put the register directly onto the output bus on a go_write
+        with m.If((self.go_wr_i):
             comb += self.data_o.eq(data_r)
 
         # put the register directly onto the address bus

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 58bb131e362da488accaa41649638df9f8762e0d..186108dc4cc05474f48b0ebd435024f14cefaf32 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -552,7 +552,6 @@ class Scoreboard(Elaboratable):
         reset_b = Signal(cul.n_units, reset_less=True)
         sync += reset_b.eq(cul.go_st_i | cul.go_wr_i | cul.go_die_i)
 
-
         comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs
         comb += memfus.addr_en_i.eq(cul.adr_rel_o) # Match enable on adr rel
         comb += memfus.addr_rs_i.eq(reset_b) # reset same as LDSTCompUnit
@@ -585,7 +584,7 @@ class Scoreboard(Elaboratable):
                                   cul.sto_rel_o & cul.st_o)
         comb += memfus.go_ld_i.eq(go_ld_i)
         comb += memfus.go_st_i.eq(go_st_i)
-        #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_nomatch_o)
+        #comb += cul.go_wr_i.eq(go_ld_i)
         comb += cul.go_st_i.eq(go_st_i)
 
         #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus])
@@ -1153,7 +1152,7 @@ def scoreboard_sim(dut, alusim):
 
         if True: # LD/ST test (with immediate)
             instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) )
-            instrs.append( (1, 2, 7, 0x12, 1, 1, (0, 0)) )
+            #instrs.append( (1, 2, 7, 0x10, 1, 1, (0, 0)) )
 
         if False:
             instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )