dcache Elif used where If should have been

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 4500d55fa565ec154b60c8181ffc2175b0ab1b9f..cd1946b7f3ad13ebf7dcac7ba446f86a423d0771 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1039,8 +1039,8 @@ class DCache(Elaboratable):
 
             # Slow ops (load miss, NC, stores)
             with m.If(r1.slow_valid):
-                sync += Display("completing store or load miss data=%x",
-                                data_out)
+                sync += Display("completing store or load miss adr=%x data=%x",
+                                r1.req.real_addr, data_out)
 
         with m.Else():
             # Request came from MMU
@@ -1474,7 +1474,7 @@ class DCache(Elaboratable):
                         sync += r1.wb.dat.eq(req.data)
                         sync += r1.wb.sel.eq(req.byte_sel)
 
-                    with m.Elif((adjust_acks < 7) & req.same_tag &
+                    with m.If((adjust_acks < 7) & req.same_tag &
                                 ((req.op == Op.OP_STORE_MISS)
                                  | (req.op == Op.OP_STORE_HIT))):
                         sync += r1.wb.stb.eq(1)
@@ -1865,7 +1865,7 @@ if __name__ == '__main__':
     test_dcache(mem, dcache_sim, "")
 
     mem = []
-    memsize = 16384
+    memsize = 256
     for i in range(memsize):
         mem.append(i)