disable transparent=False for now

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index 853e2c80afe456e6c9867a1fdea384dedb7f525d..eebd16e0dc9bf9678bc1b44d342f55a3f1218c24 100644 (file)
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -277,7 +277,7 @@ class LDSTCompUnit(Elaboratable):
             rdport = self.mem.rdport
             comb += rdport.addr.eq(self.addr_o)
             comb += self.data_o.eq(rdport.data)
-            comb += rdport.en.eq(1)
+            # comb += rdport.en.eq(1) # only when transparent=False
 
         return m
 

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 72b1a2833db3cadb3abf661a1fefd3816d46c1fe..05101d0e3f8bbb9456dfbfc2dfd5a623dd13a923 100644 (file)
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -6,7 +6,7 @@ class TestMemory(Elaboratable):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
-        self.rdport = self.mem.read_port(transparent=False)
+        self.rdport = self.mem.read_port() # not now transparent=False)
         self.wrport = self.mem.write_port()
 
     def elaborate(self, platform):