freedreno: Fix CP_COND_REG_EXEC bit positions

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>

diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index 78847fbc0210a44f5001bab90176cc5439974fc6..86c4ff0c5f3b5e9165e991cfd6cf653ea64dd350 100644 (file)
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -1473,11 +1473,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
                -->
 
                <!-- RM6_BINNING -->
-               <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
+               <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
                <!-- all others -->
-               <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
+               <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
                <!-- RM6_BYPASS -->
-               <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
+               <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
 
                <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
        </reg32>