Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index eb4461e061313f80665aced8adf91a70de3b4482..6265fcbc7ced241c3cb304e444f57374a39dcc2c 100644 (file)
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -78,7 +78,7 @@ class DivOutputStage(PipeModBase):
         with m.If(op.is_32bit):
             calc_overflow(self.i.dive_abs_overflow_32, 0x8000_0000)
         with m.Else():
-            calc_overflow(self.i.dive_abs_overflow_32, 0x8000_0000_0000_0000)
+            calc_overflow(self.i.dive_abs_overflow_64, 0x8000_0000_0000_0000)
 
         ##########################
         # main switch for DIV