add zero_a flag to CompALUOpSubset

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index 41a40ebfe307f433ce2b5fbcf194f62163da2d37..d8a9be14fcc16014876d6c0f1d34541a4f3a572c 100644 (file)
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -20,6 +20,7 @@ class CompALUOpSubset(Record):
                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
                   ('invert_a', 1),
+                  ('zero_a', 1),
                   ('invert_out', 1),
                   ('input_carry', CryIn),
                   ('output_carry', 1),
@@ -40,6 +41,7 @@ class CompALUOpSubset(Record):
         #self.cr = Signal(32, reset_less = True
         #self.xerc = XerBits(
         self.lk.reset_less = True
+        self.zero_a.reset_less = True
         self.invert_a.reset_less = True
         self.invert_out.reset_less = True
         self.input_carry.reset_less = True