halve the number of icache lines for now

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 03c3f4a3c79b3fb5fe47e96f98987145a0b231cf..9481eb7f262744d66b921770e0a4f63275fe796d 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -60,7 +60,7 @@ LINE_SIZE      = 64
 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
 ROW_SIZE       = WB_DATA_BITS // 8
 # Number of lines in a set
-NUM_LINES      = 32
+NUM_LINES      = 16
 # Number of ways
 NUM_WAYS       = 4
 # L1 ITLB number of entries (direct mapped)