Added one-clock generated add.vst.

diff --git a/experiments10/non_generated/add.vst b/experiments10/non_generated/add.vst
new file mode 100644 (file)
index 0000000..e886f75
--- /dev/null
+++ b/experiments10/non_generated/add.vst
@@ -0,0 +1,352 @@
+
+-- =======================================================================
+-- Coriolis Structural VHDL Driver
+-- Generated on Oct 25, 2020, 21:25
+-- 
+-- To be interoperable with Alliance, it uses it's special VHDL subset.
+-- ("man vhdl" under Alliance for more informations)
+-- =======================================================================
+
+entity add is
+  port ( clk : in bit
+       ; rst : in bit
+--     ; tck : in bit
+       ; tdi : in bit
+       ; tms : in bit
+       ; a   : in bit_vector(3 downto 0)
+       ; b   : in bit_vector(3 downto 0)
+       ; tdo : out bit
+       ; f   : out bit_vector(3 downto 0)
+       ; vdd : linkage bit
+       ; vss : linkage bit
+       );
+end add;
+
+architecture structural of add is
+
+  component na2_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; nq  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component noa22_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; i2  : in bit
+         ; nq  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component ao22_x2
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; i2  : in bit
+         ; q   : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component nxr2_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; nq  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component no2_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; nq  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component nao22_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; i2  : in bit
+         ; nq  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component a2_x2
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; q   : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component no3_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; i2  : in bit
+         ; nq  : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component xr2_x1
+    port ( i0  : in bit
+         ; i1  : in bit
+         ; q   : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component sff1_x4
+    port ( ck  : in bit
+         ; i   : in bit
+         ; q   : out bit
+         ; vdd : in bit
+         ; vss : in bit
+         );
+  end component;
+
+  component jtag
+    port ( clk    : in bit
+         ; rst    : in bit
+         ; tck    : in bit
+         ; tdi    : in bit
+         ; tms    : in bit
+         ; sr0__i : in bit_vector(2 downto 0)
+         ; tdo    : out bit
+         ; sr0__o : out bit_vector(2 downto 0)
+         ; vdd    : linkage bit
+         ; vss    : linkage bit
+         );
+  end component;
+
+  signal abc_1388_new_n14 :  bit;
+  signal abc_1388_new_n15 :  bit;
+  signal abc_1388_new_n17 :  bit;
+  signal abc_1388_new_n18 :  bit;
+  signal abc_1388_new_n19 :  bit;
+  signal abc_1388_new_n21 :  bit;
+  signal abc_1388_new_n22 :  bit;
+  signal abc_1388_new_n23 :  bit;
+  signal abc_1388_new_n24 :  bit;
+  signal abc_1388_new_n25 :  bit;
+  signal abc_1388_new_n26 :  bit;
+  signal abc_1388_new_n28 :  bit;
+  signal abc_1388_new_n29 :  bit;
+  signal abc_1388_new_n30 :  bit;
+  signal jtag_sr0__i      :  bit_vector(2 downto 0);
+  signal f_next           :  bit_vector(3 downto 0);
+
+
+begin
+
+  subckt_9_no2_x1 : no2_x1
+  port map ( i0  => a(2)
+           , i1  => b(2)
+           , nq  => abc_1388_new_n23
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_7_nao22_x1 : nao22_x1
+  port map ( i0  => abc_1388_new_n14
+           , i1  => abc_1388_new_n18
+           , i2  => abc_1388_new_n17
+           , nq  => abc_1388_new_n21
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_2_ao22_x2 : ao22_x2
+  port map ( i0  => b(0)
+           , i1  => a(0)
+           , i2  => abc_1388_new_n15
+           , q   => f_next(0)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_22_jtag : jtag
+  port map ( clk    => clk
+           , rst    => rst
+           , tck    => clk
+           , tdi    => tdi
+           , tms    => tms
+           , sr0__i => jtag_sr0__i(2 downto 0)
+           , tdo    => tdo
+           , sr0__o => jtag_sr0__i(2 downto 0)
+           , vdd    => vdd
+           , vss    => vss
+           );
+
+  subckt_8_a2_x2 : a2_x2
+  port map ( i0  => a(2)
+           , i1  => b(2)
+           , q   => abc_1388_new_n22
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_5_nxr2_x1 : nxr2_x1
+  port map ( i0  => abc_1388_new_n18
+           , i1  => abc_1388_new_n14
+           , nq  => abc_1388_new_n19
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_3_na2_x1 : na2_x1
+  port map ( i0  => a(1)
+           , i1  => b(1)
+           , nq  => abc_1388_new_n17
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_1_noa22_x1 : noa22_x1
+  port map ( i0  => b(0)
+           , i1  => a(0)
+           , i2  => rst
+           , nq  => abc_1388_new_n15
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_0_na2_x1 : na2_x1
+  port map ( i0  => a(0)
+           , i1  => b(0)
+           , nq  => abc_1388_new_n14
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_13_no3_x1 : no3_x1
+  port map ( i0  => abc_1388_new_n26
+           , i1  => abc_1388_new_n25
+           , i2  => rst
+           , nq  => f_next(2)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_14_xr2_x1 : xr2_x1
+  port map ( i0  => a(3)
+           , i1  => b(3)
+           , q   => abc_1388_new_n28
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_19_sff1_x4 : sff1_x4
+  port map ( ck  => clk
+           , i   => f_next(1)
+           , q   => f(1)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_21_sff1_x4 : sff1_x4
+  port map ( ck  => clk
+           , i   => f_next(3)
+           , q   => f(3)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_10_no2_x1 : no2_x1
+  port map ( i0  => abc_1388_new_n23
+           , i1  => abc_1388_new_n22
+           , nq  => abc_1388_new_n24
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_11_a2_x2 : a2_x2
+  port map ( i0  => abc_1388_new_n24
+           , i1  => abc_1388_new_n21
+           , q   => abc_1388_new_n25
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_15_ao22_x2 : ao22_x2
+  port map ( i0  => abc_1388_new_n22
+           , i1  => abc_1388_new_n25
+           , i2  => abc_1388_new_n28
+           , q   => abc_1388_new_n29
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_16_no3_x1 : no3_x1
+  port map ( i0  => abc_1388_new_n28
+           , i1  => abc_1388_new_n25
+           , i2  => abc_1388_new_n22
+           , nq  => abc_1388_new_n30
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_17_no3_x1 : no3_x1
+  port map ( i0  => abc_1388_new_n30
+           , i1  => abc_1388_new_n29
+           , i2  => rst
+           , nq  => f_next(3)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_18_sff1_x4 : sff1_x4
+  port map ( ck  => clk
+           , i   => f_next(0)
+           , q   => f(0)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_6_no2_x1 : no2_x1
+  port map ( i0  => abc_1388_new_n19
+           , i1  => rst
+           , nq  => f_next(1)
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_4_nxr2_x1 : nxr2_x1
+  port map ( i0  => a(1)
+           , i1  => b(1)
+           , nq  => abc_1388_new_n18
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_12_no2_x1 : no2_x1
+  port map ( i0  => abc_1388_new_n24
+           , i1  => abc_1388_new_n21
+           , nq  => abc_1388_new_n26
+           , vdd => vdd
+           , vss => vss
+           );
+
+  subckt_20_sff1_x4 : sff1_x4
+  port map ( ck  => clk
+           , i   => f_next(2)
+           , q   => f(2)
+           , vdd => vdd
+           , vss => vss
+           );
+
+end structural;
+