add extra "modes" to PortInterface

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 3fac8cb649354b110779a250ee71935106065240..89ba7714dc85a0d816d2e338a1cfffc18b4520ab 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -113,6 +113,12 @@ class PortInterface(RecordObject):
         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 
+        # additional "modes"
+        self.dcbz          = Signal()  # data cache block zero request
+        self.nc            = Signal()  # no cacheing
+        self.virt_mode     = Signal()  # virtual mode
+        self.priv_mode     = Signal()  # privileged mode
+
     def connect_port(self, inport):
         print("connect_port", self, inport)
         return [self.is_ld_i.eq(inport.is_ld_i),