working on all cycles, RaW / WaR

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index cab033bee236b19bd4c857ad3f5e428d7f9d8a08..9e17b3f2a516e470b569b731b8937ac6e8b3bed5 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -417,8 +417,6 @@ def scoreboard_sim(dut, alusim):
             yield
         yield from print_reg(dut, [1,2,3])
         yield
-        yield
-        yield
 
     yield
     yield from print_reg(dut, [1,2,3])

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 9a54e3a4b4f7f4a21c06f9038f92fa9fbe016687..649b44e283c1976a78f5c32afdbd65329294462f 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -51,7 +51,7 @@ class DepCell(Elaboratable):
         m.d.comb += l.r.eq(self.go_i)
 
         # Function Unit "Forward Progress".
-        m.d.comb += self.fwd_o.eq((cq | l.q) & self.hazard_i & ~self.issue_i)
+        m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i)# & ~self.issue_i)
 
         # Register Select. Activated on go read/write and *current* latch set
         m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)