allow Pi2LSUI to accept incoming PortInterface and LoadStoreUnitInterface

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 97a42c860a462b75f2e834ee431ac3bc75e1d2c0..b1c888d12c08ba499faaff39d29f2e040309b392 100644 (file)
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -31,10 +31,14 @@ from nmigen import Elaboratable, Module, Signal
 
 class Pi2LSUI(Elaboratable):
 
-    def __init__(self, name, regwid=64, addrwid=48):
+    def __init__(self, name, pi=None, lsui=None, regwid=64, addrwid=48):
         self.addrbits = 4
-        self.pi = PortInterface(name="%s_pi", regwid, addrwid)
-        self.lsui = LoadStoreUnitInterface(addrwid, self.addrbits, regwid)
+        if pi is None:
+            pi = PortInterface(name="%s_pi", regwid, addrwid)
+        self.pi = pi
+        if lsui = None:
+            lsui = LoadStoreUnitInterface(addrwid, self.addrbits, regwid)
+        self.lsui = lsui
 
     def splitaddr(self, addr):
         """split the address into top and bottom bits of the memory granularity