dewildcardify units

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 45d7487205184df77570cf4232168927d88d2391..b140aa20d300b4b837552a8e124928b2d8efd2f8 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -1,8 +1,8 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Record
 from nmigen.utils import log2_int
 
-from ..cache import *
-from ..wishbone import *
+from ..cache import L1Cache
+from ..wishbone import wishbone_layout
 
 
 __all__ = ["PCSelector", "FetchUnitInterface", "BareFetchUnit", "CachedFetchUnit"]

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index 0fe92f0c8b44ae5273ed48b81dbf5b669fd6ee6c..ac2a042685744ffa2e3b191b8412f2bc3e359e7f 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -1,10 +1,10 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Record, Cat
 from nmigen.utils import log2_int
 from nmigen.lib.fifo import SyncFIFO
 
-from ..cache import *
+from ..cache import L1Cache
 from ..isa import Funct3
-from ..wishbone import *
+from ..wishbone import wishbone_layout
 
 
 __all__ = ["DataSelector", "LoadStoreUnitInterface", "BareLoadStoreUnit", "CachedLoadStoreUnit"]

diff --git a/src/soc/minerva/units/logic.py b/src/soc/minerva/units/logic.py
index fe96ede1dd697bae5a380abdf234b499fee76269..143cd7f842756ac329533dd4730a8b1c870c1995 100644 (file)
--- a/src/soc/minerva/units/logic.py
+++ b/src/soc/minerva/units/logic.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal
 
 from ..isa import Funct3
 

diff --git a/src/soc/minerva/units/multiplier.py b/src/soc/minerva/units/multiplier.py
index 80e7a0c0aaa5cd2c12fa15c81674bf057bb7bff5..c79d987ef290352ff5e201712b82cf62ebee68af 100644 (file)
--- a/src/soc/minerva/units/multiplier.py
+++ b/src/soc/minerva/units/multiplier.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Cat, Mux
 
 from ..isa import Funct3
 

diff --git a/src/soc/minerva/units/predict.py b/src/soc/minerva/units/predict.py
index f56179031b4faa1fa6a25133976595b0a84a5b1b..b95deaaab98c411e8b6c55b7e6747ddbe1289061 100644 (file)
--- a/src/soc/minerva/units/predict.py
+++ b/src/soc/minerva/units/predict.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal
 
 
 __all__ = ["BranchPredictor"]

diff --git a/src/soc/minerva/units/rvficon.py b/src/soc/minerva/units/rvficon.py
index 6442ef51fcae8f5d10dde0a0291bc534de99ce09..266fd12ac51136b86e273d6c4f019cc595e3f456 100644 (file)
--- a/src/soc/minerva/units/rvficon.py
+++ b/src/soc/minerva/units/rvficon.py
@@ -1,11 +1,10 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
+from nmigen.hdl.rec import DIR_FANOUT
 
-from ..isa import *
-from ..wishbone import *
+from ..wishbone import wishbone_layout
 
 
 __all__ = ["rvfi_layout", "RVFIController"]

diff --git a/src/soc/minerva/units/shifter.py b/src/soc/minerva/units/shifter.py
index c6a2ed0f28d6487548dd5e1244f0b161443e292a..4ecd9fc008a26ce2f30301a302fe23257fef7aa6 100644 (file)
--- a/src/soc/minerva/units/shifter.py
+++ b/src/soc/minerva/units/shifter.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Mux, Repl, Cat
 
 
 __all__ = ["Shifter"]

diff --git a/src/soc/minerva/units/trigger.py b/src/soc/minerva/units/trigger.py
index 147c0cd07e9d4b0c0e85da2e2079e8ddd74c6f3d..203b608111cba13847f465e840d2c67cd9201af3 100644 (file)
--- a/src/soc/minerva/units/trigger.py
+++ b/src/soc/minerva/units/trigger.py
@@ -1,11 +1,10 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
 
-from ..csr import *
-from ..isa import *
+from ..csr import AutoCSR, CSR
+from ..isa import flat_layout, tdata1_layout
 
 
 __all__ = ["TriggerUnit"]