select a firmware file

diff --git a/examples/soc.py b/examples/soc.py
index c688e08f51eac9c86bcb2cec7bad942112b05400..2389e07a13f8eb13602b86c817cc223ede9726d2 100644 (file)
--- a/examples/soc.py
+++ b/examples/soc.py
@@ -147,8 +147,9 @@ class DDR3SoC(SoC, Elaboratable):
 if __name__ == "__main__":
 
     # create a platform selected from the toolchain. defaults to VERSA_ECP5
+    # only VERSA_ECP5 will work for now because of the DDR3 module
     fpga = "versa_ecp5"
-    if len(sys.argv) == 2:
+    if len(sys.argv) >= 2:
         fpga = sys.argv[1]
     platform_kls =  {'versa_ecp5': VersaECP5Platform,
                      'ulx3s': ULX3S_85F_Platform,
@@ -160,6 +161,13 @@ if __name__ == "__main__":
                 }.get(fpga, None)
     platform = platform_kls(toolchain=toolchain)
 
+    # select a firmware file
+    firmware = None
+    fw_addr = None
+    if len(sys.argv) >= 3:
+        firmware = sys.argv[2]
+        fw_addr = 0x0000_0000
+
     # get DDR and UART resource pins
     ddr_pins = platform.request("ddr3", 0,
                                 dir={"dq":"-", "dqs":"-"},
@@ -171,9 +179,10 @@ if __name__ == "__main__":
     soc = DDR3SoC(ddrphy_addr=0xff000000, # DRAM firmware init base
                   dramcore_addr=0x80000000,
                   ddr_addr=0x10000000,
+                  fw_addr=fw_addr,
                   ddr_pins=ddr_pins,
                   uart_pins=uart_pins,
-                  fw_addr=None)
+                  firmware=firmware)
 
     # build and upload it
     platform.build(soc, do_program=True)