fake up wishbone stall signal in icache.

same thing is done in dcache

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index f84775622c4e9a4c8a704978cfe92188a72535e7..cf95633f19a3926811d8c4ec3dd18e7b0ff0e089 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -834,6 +834,10 @@ class ICache(Elaboratable):
         plru_victim      = PLRUOut()
         replace_way      = Signal(WAY_BITS)
 
+        # fake-up the wishbone stall signal to comply with pipeline mode
+        # same thing is done in dcache.py
+        comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
+
         # call sub-functions putting everything together,
         # using shared signals established above
         self.rams(m, r, cache_out_row, use_previous, replace_way, req_row)